[specify_block]

Endmodule

range ::= [constexpr : constexpr]

parameter {PARID = constexpr,};

wire | wand | wor [range] {WIRID,};

reg [range] {REGID [range],};

integer {INTID [range],};

time {TIMID [range],};

real {REALID,};

realtime {REALTIMID,};

event {EVTID,};

task TASKID;

[{input | output | inout [range] {ARGID,};}]

[{declaration}]

[{sequential_statement}]

assign [(strength1, strength0)] WIRID = expr;

initial sequential_statement

always sequential_statement

MODID [#({expr,})] INSTID

([{expr,} | {.PORTID(expr),}]);

GATEID [(strength1, strength0)] [#delay]

[INSTID] ({expr,});

defparam {HIERID = constexpr,};

strength ::= supply | strong | pull | weak | highz

delay ::= number | PARID | ( expr [, expr [, expr]] )

GATE PRIMITIVES

and (out, in1, ..., inN);

nand (out, in1, ..., inN);

or (out, in1, ..., inN);

nor (out, in1, ..., inN);

xor (out, in1, ..., inN);

xnor (out, in1, ..., inN);

buf (out1, ..., outN, in);

not (out1, ..., outN, in);

bufif1 (out, in, ctl);

bufif0 (out, in, ctl);

notif1 (out, in, ctl);

notif0 (out, in, ctl);

pullup (out);

pulldown (out);

[r]pmos (out, in, ctl);

[r]nmos (out, in, ctl);

[r]cmos (out, in, nctl, pctl);

[r]tran (inout, inout);

[r]tranif1 (inout, inout, ctl);

[r]tranif0 (inout, inout, ctl);

SEQUENTIAL STATEMENTS

begin[: BLKID

[{declaration}]]

[{sequential_statement}]

if (expr) sequential_statement

[else sequential_statement]

case | casex | casez (expr)

[{{expr,}: sequential_statement}]

[default: sequential_statement]

forever sequential_statement

repeat (expr) sequential_statement

while (expr) sequential_statement

for (lvalue = expr; expr; lvalue = expr)

sequential_statement

#(number | (expr)) sequential_statement

@ (event [{or event}]) sequential_statement

lvalue [<]= [#(number | (expr))] expr;

lvalue [<]= [@ (event [{or event}])] expr;wait (expr) sequential_statement

-> EVENTID;

fork[: BLKID

[{declaration}]]

[{sequential_statement}]

TASKID[({expr,})];

disable BLKID | TASKID;

assign lvalue = expr;

deassign lvalue;

lvalue ::=

ID[range] | ID[expr] | {{lvalue,}}

event ::= [posedge | negedge] expr

{specify_statement}

endspecify

SPECIFY BLOCK STATEMENTS

specparam {ID = constexpr,};

((terminal,} *> {terminal,}) = path_delay;

if (expr) (terminal [+|-]=> terminal) = path_delay;

if (expr) ({terminal,} [+|-]*> {terminal,}) =

[if (expr)] ([posedge|negedge] terminal =>

(terminal [+|-]: expr)) = path_delay;

[if (expr)] ([posedge|negedge] terminal *>

({terminal,} [+|-]: expr)) = path_delay;

$setup(tevent, tevent, expr [, ID]);

$hold(tevent, tevent, expr [, ID]);

$setuphold(tevent, tevent, expr, expr [, ID]);

$period(tevent, expr [, ID]);

$width(tevent, expr, constexpr [, ID]);

$skew(tevent, tevent, expr [, ID]);

$recovery(tevent, tevent, expr [, ID]);

tevent ::= [posedge | negedge] terminal

[&&& scalar_expr]

path_delay ::=

expr | (expr, expr [, expr [, expr, expr, expr]])

terminal ::= ID[range] | ID[expr]

unop primary

expr binop expr

expr ? expr : expr

primary ::=

literal | lvalue | FCTID({expr,}) | ( expr )

UNARY OPERATORS

.
+, - Positive, Negative.

! Logical negation.

~ Bitwise negation

.

&, ~& Bitwise and, nand

.

|, ~| Bitwise or, nor

. 

^, ~^, ^~ Bitwise xor, xnor

. 

?: if/else

. 

|| Logical or

. 

&& Logical and

. 

| Bitwise or

. 

^, ^~ Bitwise xor, xnor

.

& Bitwise and

.

==, != , ===, !== Equality

.

= Inequality

.

Logical shift.

 .

+, - Addition, Subtraction.

 .

*, /, % Multiply, Divide, Modulo.

 .

SIZES OF EXPRESSIONS

sized constant as specified.

i op j +,-,*,/,%,&,|,^,^~ max(L(i), L(j))

. 

op i +, -, ~ L(i)

.

i op j ===, !==, ==, !=

.

&&, ||, >, >=, <, <= 1

.

op i &, ~&, |, ~|, ^, ~^ 1

.

i op j >>, << L(i)

.

i ? j : k max(L(j), L(k))

. 

{i,...,j} L(i) + ... + L(j)

.

{i{j,...k}} i * (L(j)+...+L(k))

.

i = j L(i)

.