Introduction
Writing a testbench is as complex as writing the RTL code itself. These days ASICs are getting more and more complex and thus verifying these complex ASIC has become a challenge. Typically 60-70% of time needed for any ASIC is spent on verification/validation/testing. 

Even though the above facts are well known to most ASIC engineers, still engineers think that there is no glory in verification.

  1 //-----------------------------------------------------

  2 // Design Name : counter

  3 // File Name   : counter.v

  4 // Function    : 4 bit up counter

  5 // Coder       : Deepak

  6 //-----------------------------------------------------

  7 module counter (clk, reset, enable, count);

  8 input clk, reset, enable;

  9 output [3:0] count;

 10 reg [3:0] count;                                  

 11

 12 always @ (posedge clk)

 13 if (reset == 1'b1) begin

 14   count <= 0;

 15 end else if ( enable == 1'b1) begin

 16   count <= count + 1;

 17 end

 18

 19 endmodule

Test Plan 
We will write a self-checking test bench, but we will do this in steps to help you understand the concept of writing automated test benches. Our testbench environment will look something like the figure below.

Test Cases

• Reset Test : We can start with reset de-asserted, followed by asserting reset for few clock ticks and deasserting the reset, See if counter sets its output to zero.
• Enable Test : Assert/deassert enable after reset is applied.
• Random Assert/deassert of enable and reset.