Port Connection Rules

Inputs : internally must always be of type net, externally the inputs can be connected to a variable of type reg or net.

Outputs : internally can be of type net or reg, externally the outputs must be connected to a variable of type net.

Inouts : internally or externally must always be type net, can only be connected to a variable net type.

• Width matching : It is legal to connect internal and external ports of different sizes. But beware, synthesis tools could report problems.
• Unconnected ports : unconnected ports are allowed by using a ",".
• The net data types are used to connect structure.
• A net data type is required if a signal can be driven a structural connection.

Example - Implicit Unconnected Port

  1 module implicit();

  2 reg clk,d,rst,pre;

  3 wire q;

  4

  5 // Here second port is not connected

  6 dff u0 ( q,,clk,d,rst,pre);

  7

  8 endmodule

  9

 10 // D fli-flop

 11 module dff (q, q_bar, clk, d, rst, pre);

 12 input clk, d, rst, pre;

 13 output q, q_bar;

 14 reg q;

 15

 16 assign q_bar = ~q;

 17

 18 always @ (posedge clk)

 19 if (rst == 1'b1) begin

 20   q <= 0;

 21 end else if (pre == 1'b1) begin

 22   q <= 1;

 23 end else begin

 24   q <= d;

 25 end

 26

 27 endmodule

Example - Explicit Unconnected Port

  1 module explicit();

  2 reg clk,d,rst,pre;

  3 wire q;

  4

  5 // Here q_bar is not connected

  6 // We can connect ports in any order

  7 dff u0 ( 

  8 .q         (q),

  9 .d (d),

 10 .clk       (clk),

 11 .q_bar     (),

 12 .rst       (rst),

 13 .pre       (pre)

 14 );

 15

 16 endmodule

 17

 18 // D fli-flop

 19 module dff (q, q_bar, clk, d, rst, pre);

 20 input clk, d, rst, pre;

 21 output q, q_bar;

 22 reg q;

 23

 24 assign q_bar = ~q;

 25

 26 always @ (posedge clk)

 27 if (rst == 1'b1) begin

 28   q <= 0;

 29 end else if (pre == 1'b1) begin

 30   q <= 1;

 31 end else begin

 32   q <= d;

 33 end

 34

 35 endmodule

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