Coming soon with OOB questions and answer . stay tuned.

Please leave your comments if you want to add logical question or have any doubt.

Q1. Design a Lift controller. Below are the specification.

How to pass parameter in verilog design from the top module ?

There are different method to do that , when a module is instantiate with different usage, probably width is one of the parameter which may not be same for all instantiation.

We all know that there are blocking statements and non-blocking statements ,  If I ask what is blocking and what is non-blocking , the first answer I used to get is , blocking used in combinational circuits and non-blocking used in sequential circuit.

Left edge and dogleg algorithm comes under detailed routing where it determines the exact route and layers for each net. These algorithm helps in minimizing the area (congestion).

BIST generates its own stimulus and analyzes its own response.  BIST is used normally to validate a product in labs, there are different kind of BIST used in system to validate.
one of the method is , using LFSR, LFSR generates random stimulus and it is expected that chip is in its normal functional mode. with the configuration, with LFSR ,

Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.

In order to create a DC-balanced data stream, the concept of disparity is employed to balance the number of 0s and 1s. 

Q ASYNC OR SYNC RESET? which one is use more in ASIC industry?

Async reset with sync release is probably the most common. Sync reset is used occasionally though. Async has the obvious advantage that your PoR works before the clock is working. You need a sync release to avoid potential metastability and make sure FSM start in a consistent state.

Introduction:

A Mixed Signal Interface could be a high speed interface where data is transferred between two devices through a medium. Transmitting data is not big issue but receiving data contribute major part of its performance. Key points/block for high speed and high performance mixed signals are described in below sections.

Each cell in design will have timing arcs, there are different types of arcs present in design. For example, for sequential cell , timing arc will be from clock to Q , for Combi logic, timing arc will be from input to output.

This section will tell you how to dump the list of sync cell using spyglass tool.

There are complexities and different settings which depends on design to design, some fine tuning may require to dump the Synchronizer list.


Spyglass give a lot of options which vary design to design, below are the common settings you can use in spyglass project file.

Asynchronous FIFO Design
Asynchronous FIFO Verilog Code
Asynchronous FIFO with block diagram and verilog Code.

In the case of even parity, the number of bits whose value is 1 in a given set are counted. If that total is odd, the parity bit value is set to 1, making the total count of 1's in the set an even number. If the count of ones in a given set of bits is already even, the parity bit's value remains 0.

Detecting pattern is come in Digital design and it is most commonly question during the interview.

Here is one example of detecting " 100110 " pattern using a FSM.