Introduction: A Mixed Signal Interface could be a high speed interface where data is transferred between two devices through a medium. Transmitting data is not big issue but receiving data contribute major part of its performance. Key points/block for high speed and high performance mixed signals are described in below sections.
Major Blocks in Mixed Signal Design which decides the performance of design:
A. CDR (Clock Data Recovery)
CDR is major block of receiver, it is Clock and Data recovery circuit. It is very important the behavioral model of CDR must be accurate to measure the overall performance.
B .DFE (Decision Feedback Equalizer)
Decision Feedback Equalizer is also a major part of mixed signal design if you are talking about performance. This block is useful if data rate is more than 10 Gbps. This block remove the ISI from incoming signal. This is one of the most complicated design in high speed mixed signal design.
C. TX Driver
When you are driving signal on physical medium, then this block play a major role in it. This block drive signal with perfect strength, voltage level, and other factor which are dependent on physical medium, for example 12inch cable , 24 inch cable. It is called channel.
Each channel is having it’s own properties and Tx driver has to adapt those properties to transmit signal with minimum loss and adding noise in that signal.
Key Points in Mixed Signal Verification:
1. Assertion
Assertion play a major role in mixes signal verification, especially on the analog/digital interface. Most of the signals going into analog domain, are asynchronous in nature but there are dependencies with other signals. One should understand the interface carefully and write assertion based on the behavior of the signal.
2. BFM:
BFM plays a critical role to verify mixed signal design. To verify the mixed signal design , behavioral model of analog block must be close be actual behavioral of block.
BFM part can be divided in 2 parts.
A. Functional Simulation
Functional simulation will have 1-bit ports as physical medium and this can be tested with CDR BFM to receive data, no noise injection or ISI will be seen on signal as it is 1-bit signal. Here one can verify the Protocol but not performance.
B. Behavioral Simulation
In System Verilog, a ports can be define as real port , So physical interface ( Tx and Rx serial lines) can be instantiate as real ports in TB. This should support inside design also.
On TB having real ports, one can write some BFM which can inject noise, and ability to distort the signal. Noise injection and distortion should be controllable in test bench.
This part of functional simulation is very important as it measure the performance of design. The behavior model (BFM) can have algorithm to inject noise into incoming signal (on Rx serial line of design). Basically there are adaptation and calibration algorithm in mixed signal design which are very much rely on incoming signal on real port. In side analog block, there is serial to parallel conversion, where Rx clock from CDR block is used
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