Resolved Logic Vectors
In real hardware, there are times when we need to model tristate bus. So that multiple agents can drive same bus. Like PCI bus or Microprocessor 8085 address and data bus.

To help with this SystemC provides Resovled Logic Vectors. In this agent which is driving 0, 1 win's the bus. In the below image, we have Module A driving 1 and Module B driving Z. Resolve signal Y gets 1.

When Module A drives 1 and Module B drives 0, then output Y is X. X denotes Unknown value.

Resolve of Logic Values

Example : Resolved Logic Vectors

  1 #include 

  2 

  3 SC_MODULE(module_A) {

  4   sc_in_rv<1>  in;

  5   sc_out_rv<1> out;

  6   sc_inout_rv<4> inout;

  7 

  8   void body () {

  9     out.write(in);

 10     if (in.read() == 1) {

 11       out.write(1);

 12       inout.write(rand());

 13     } else {

 14       out.write('z');

 15       inout.write('zzzz');

 16     }

 17   }

 18  

 19   SC_CTOR(module_A) {

 20     SC_METHOD(body);

 21       sensitive << in;

 22   }

 23 };

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