# Trung tâm đào tạo thiết kế vi mạch Semicon

• Đăng ký
 Name: * Tên đăng nhập: * Email: * Mật khẩu: * Verify Password: * Fields marked with an asterisk (*) are required.

## Combinational Arithmetic Circuits Part-II

An n-bit adder used to add two n-bit binary numbers can be built by connecting n full adders in series. Each full adder represents a bit position j (from 0 to n-1).

Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at higher position j+1. The output of a full adder at position j is given by: Sj= Xj   Yj   Cj
Cj+1 = Xj . Yj + Xj . Cj + Y . Cj

In the expression of the sum Cj must be generated by the full adder at lower position j. The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately:

Total Propagation delay = 2 nD

X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3
Total Propagation delay = 2 nD = 8D or 8 gate delays

Example: 16-bit adder using 4 4-bit adders. Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from the most significant position.

 Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 nD = 4 x 8D = 32 D or 32 gate delays

• Add the two 4-bit BCD code inputs.
• Determine if the sum of this addition is greater than 1001; if yes, then add 0110 to this sum and generate a carry to the next decimal position.
.
 Â

Bạn Có Đam Mê Với Vi Mạch hay Nhúng      -     Bạn Muốn Trau Dồi Thêm Kĩ Năng

# Hãy Để Chúng Tôi Hỗ Trợ Cho Bạn. SEMICON

Lần cập nhật cuối ( Thứ ba, 29 Tháng 3 2022 00:15 )