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Tài Liệu Luyện GRE
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Thư Viện Sơ Đồ Khối IP - IP Block Diagram Library
Sample Projects Download
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Uncategorized
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x86 Compatible SOC with Video , keyboard , GPIO , uart
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X.25 interface core
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wishbone_checker
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Wishbone to NPI core
. .
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VoIP Smart IP Phone SI-160
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Viterbi Decoder (K=7, G=(171, 133))
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Viterbi Decoder
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Viterbi Decoder
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VHDL wavefile package
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VHDL MD5 Hash Core (Complete)
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Verilog Rijndael (AES) Implementation
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Verilator Verilog to C++/SystemC compiler
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ultravec
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Trapezoidal Shaper
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transmitter
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tindy lattic fpga project for dlp
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thocon
. .
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SystemC CORDIC
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svmac
. .
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Subtractive / Additive Synthesizer
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STS-1 soft core
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SPORT Interface implementation in VHDL for Winbond Micro controller
. .
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SPI-Slave
. .
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smallARM
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slave vme bridge
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Single cycle multiply accumulate block
. .
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simpleUart -
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Simple Interruput Controller Core
. .
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serpent_core
. .
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SEAnb
. .
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sdram_ctrl
. .
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sdram control core
. .
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SDR SDRAM Controller
. .
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SCSI Interface
. .
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RISC CPU (DLX) in SystemC
. .
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rc5
. .
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RadioHDL
. .
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Programmable DCT Accelarator with 16 bit Microcontroller
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Profibus
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pnctl
. .
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Pipelined 8-point DCT
. .
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Performance counter for Microblaze
. .
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PCI to IDE Controller core
. .
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Packet Filter
. .
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OpenTech Cd-rom
. .
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openCPU 67-80-85
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open 1394 intellectual property
. .
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OPB-compatible UDP transceiver
. .
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OPB-compatible PS/2 Keyboard Controller
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Omega CPU - Alpha like clone
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ocmips
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ntsc video encoder
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NorthBridge (PPC)
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nonrestoringsquareroot
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ngocminh
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NeoT
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Multiplierless 64 point FFT Processor
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MPEG-4 Video Coding
. .
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mips single cycle microprocessor
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Mini-ACEX1K
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mil std 1553b
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MD5 Hash Core RFC 1321
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mcu
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Matrix Determinant Processor
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Manchester Encoder / Decoder
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Macroblock Motion Detection
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LWMIPS
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LPC(Low Pin Count) controller and peripherals
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Light Uart
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ldpc
. .
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KCPSM3 Maskable Interrupt
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JPEG Decoder
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intel 8031
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I2C slave for data transfer
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High speed adder for large bit size computation
. .
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GCPU
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Function Generator
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FSL 2 Serial Peripheral
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FPGA Based PWM Inverter
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Floppy Drive Controller
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Floating Point Square Root
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floating point adder/subtractor
. .
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Fix-Point Cordic Engine
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FIR-Gen
. .
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fft_32
. .
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FastAES
. .
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eMotion NEMO Implementation
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Dallas one-wire protocol with a DS1821 top level demo
. .
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CLAW: A two way multithreaded (8 threads) VLIW Processor
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Cereon
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BRISC microprocessor
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ALU with selectable inputs and outputs
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AHB ARBITER
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AC97 Controller
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Video controller
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Yet Another VGA
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Yet another verilog VGA
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Wishbone Monitor Controller
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Wire-Frame 3D Graphics Accelerator IP Core
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Video Stream Scaler
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Video Starter Kit
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Video Dithering
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Video compression systems
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VGA/LCD Controller
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ULA chip for ZX Spectrum
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tft lcd controller
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Sharp LQ057Q3DC02 LCD Controller
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Sharp LQ057Q3DC02 LCD Controller
. .
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rtfTextController
. .
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rtfSpriteController / Hardware cursors
. .
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rtfBitmapController
. .
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ROSETTA Configurable Dot Matrix Display Controller
. .
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PAL/NTSC encoder
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OV7670 Camera Video Capturing
. .
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openGFX430
. .
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OPB-compatible VGA character display, no DAC
. .
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NPI graphics controller
. .
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MPEG2 Video decoder
. .
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Motion Estimation Processor
. .
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Monochrome Text-Mode VGA Video Display Adapter
. .
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MiniGA - High Quality PAL Encoder
. .
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Memory mapped LCD Controller (KS0073)
. .
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LCD to HDMI output IP
. .
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LCD Driver
. .
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JPEG Hardware Compressor
. .
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JPEG Encoder Verilog
. .
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JPEG Encoder
. .
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JPEG codec library based on microblaze
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Image warping/Texture mapping core
. .
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H.264/AVC Baseline Decoder
. .
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Graphics Accelerator
. .
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Graphical LCD interfaces
. .
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FlexGripPlus General Purpose Graphics Processing Unit (GPGPU) core
. .
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FastMemoryLink VGA framebuffer controller
. .
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Demosaic (Bilinear)
. .
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Color Converter
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CCITT-G4(tiff) compression
. .
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Bluespec H.264 Decoder
. .
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axi_vga
. .
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AXI4 to VGA Frame Buffer with Linux driver
. .
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16x2_lcd_display
. .
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(M)JPEG Decoder
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Testing / Verification
. .
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Wishbone Scope
. .
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Video Pattern Generator
. .
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VHDL Whisbone Test Bench
. .
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Uart2BusTestBench
. .
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UART observer
. .
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The VHDL Test Bench
. .
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SystemVerilog Directed Test Bench
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StaplPlayer
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Soundfile Testbench
. .
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socgen
. .
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SocExplorer
. .
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Simulation tools library
. .
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PRBS Signal Generator and Checker
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PlTbUtils
. .
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Open JTAG project
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LogicProbe
. .
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i2clcd
. .
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High Load configurable test project
. .
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HASM TestBench Vector Generator
. .
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Generic AXI slave stub
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Generic AXI master stub
. .
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Generic APB slave stub
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Generic APB master stub
. .
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Generic AHB slave stub
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Generic AHB master stub
. .
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FROM and TO files
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FPO (Logic Analyzer)
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EziDebug
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DS1621 model
. .
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Diagnostics library
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Constrained random test generator
. .
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c - VHDL Co-Simulation with FLI
. .
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Bus Transaction Monitor with JTAG
. .
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Boost Converter
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System controller
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Wupper: PCIe DMA Engine for Xilinx FPGAs
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WB LCD Character Display Controller
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TI DSP and Xilinx FPGA Dev Board
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Synchronous-DRAM Controller
. .
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scsi_chip
. .
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RS232 system controller
. .
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Programmable Interrupt Controller
. .
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Power Supply Sequencer
. .
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pci_mini
. .
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PCIe_mini_axi4s_wb
. .
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PCIe_mini (PCI-Express to Wishbone Bridge for Xilinx FPGAs)
. .
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PCIe_DS_DMA
. .
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PCIe SG DMA controller
. .
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PCI Target
. .
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PCI slave to WB master
. .
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PCI Express x1 16bit VERA testbench
. .
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PCI bridge
. .
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OCIDEC (OpenCores IDE Controller)
. .
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Memory Controller IP Core
. .
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External parallel port to internal wishbone master interface
. .
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AHBmaster for FPGA of microsemi
. .
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AC 97 Controller IP Core
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System on Module
. .
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SoM-ARM9-CycloneIVGX
. .
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OpenArty
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System on Chip
. .
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Zorro bus to Wishbone bridge
. .
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Z80 System on Chip
. .
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XuLA2-LX25 SoC
. .
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WishboneTK toolkit
. .
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Wishbone to AHB Bridge
. .
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Wishbone System6800/01
. .
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wishbone out port from b3 spec
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WISHBONE DMA/Bridge IP Core
. .
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WISHBONE Conmax IP Core
. .
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WISHBONE Conbus IP Core
. .
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WISHBONE Builder
. .
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WB/OPB & OPB/WB Interface Wrapper
. .
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Taar Microprocessor
. .
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System09
. .
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system05
. .
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System-on-Chip Wire (SoCWire)
. .
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System-On-Chip based on bare Rocket-chip (RISC-V ISA)
. .
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STORM SoC
. .
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Soft MultiProcessor on FPGA
. .
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Simple AXI4-Lite bridges for IPbus and Wishbone
. .
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SimpCon - a Simple SoC Interconnect
. .
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SBA - Simple Bus Architecture
. .
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SardMIPS
. .
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rtf68kSys
. .
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rfid tag and reader
. .
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Real-time image processing
. .
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PSS (Programmable Supervisor for Systems-on-Chip)
. .
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Project Oberon with SDRAM
. .
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PLBv46 to Wishbone Bridge
. .
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PIF2WB
. .
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PDP-1 reimplementation
. .
|_
ORPSoC
. .
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Or1k SoC on Altera Embedded Dev Kit
. .
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or1200_soc
. .
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OpenSPARC-based SoC
. .
|_
OpenFIRE
. .
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OpenCL Board Support Package (BSP) for the Nallatech / Bittware 385A including dual 40 Gigabit Ethernet interfaces.
. .
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OMS8051 MINI
. .
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OC - H.264 Encoder SoC
. .
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NoCmodel
. .
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NoCem -- Network on Chip emulator
. .
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NoC(Network-on-Chip) Simulator
. .
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NoC based MPSoC
. .
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Next186MP3
. .
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Next186 SoC PC
. .
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MP3 decoder
. .
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minsoc
. .
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MaSoCist Soc builder/simulator
. .
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M16C5x
. .
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layer[2]
. .
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Keras to FPGA
. .
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Internal communication bus for FPGA
. .
|_
I2C Controller Wishbone Wrapper
. .
|_
H2 Forth SoC
. .
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Generic AXI to APB bridge
. .
|_
Generic AXI to AHB bridge
. .
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Generic AXI interconnect fabric
. .
|_
Generic AXI DMA
. .
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Generic APB register file
. .
|_
Generic AHB matrix
. .
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GECKO4 SoC co-design environment
. .
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GECKO3 SoC co-design environment
. .
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Experimental Unstable CPU
. .
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EPC RFID Transponder
. .
|_
Embedded FPGA Core
. .
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Embedded 32-bit RISC uProcessor with SDRAM Controller
. .
|_
ECO32
. .
|_
CPU Lecture
. .
|_
CMOD S6 SoC
. .
|_
CCSDS RX_TX_SoC
. .
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AXI4 Transactor and Bus Functional Model
. .
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AXI DMA 32 / 64 bits
. .
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Async-SDM-NoC
. .
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Assembler with VHDL User-defined Commands (AVUC)
. .
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Arm core
. .
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aoOCS - Wishbone Amiga OCS SoC
. .
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AHB to Wishbone Bridge
. .
|_
ahb system generator
. .
|_
AHB DMA 32 / 64 bits
.
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Processor
. .
|_
ZPU - the worlds smallest 32 bit CPU with GCC toolchain
. .
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Zip Cpu
. .
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Zet - The x86 (IA-32) open implementation
. .
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ZAP
. .
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z80control
. .
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Z3 - The Zork CPU
. .
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Yellow Star
. .
|_
YACC-Yet Another CPU CPU
. .
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Y80e - Z80/Z180 compatible processor extended by eZ80 instructions
. .
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Wishbone High Performance Z80
. .
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Wishbone BFM
. .
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VTACH - Bell Labs CARDIAC reimagined in Verilog
. .
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VLIW Processor
. .
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vhdl core of IC6821
. .
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V6502
. .
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v586
. .
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UoS Educational Processor
. .
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UCore
. .
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TV80
. .
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turbo 8051
. .
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TotalCPU
. .
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tinyVLIW8
. .
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TinyCPU
. .
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tiny8
. .
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Tiny64
. .
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Tiny Instruction Set Computer
. .
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Thor Superscaler
. .
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Theia: ray graphic processing unit
. .
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The Neptune Core
. .
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TG68K.C
. .
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TG68 - execute 68000 Code
. .
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T80 cpu
. .
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T6507LP
. .
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T65 CPU
. .
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T51 mcu
. .
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T48 µController
. .
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T400 µController
. .
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System68
. .
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system11
. .
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SXP (Simple eXtensible Pipeline ) Processor
. .
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Storm Core (ARM7 compatible)
. .
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Small Stack Based Computer Compiler
. .
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Software Aided Wishbone Extension for Xilinx (R) PicoBlaze (TM)
. .
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Small x86 subset core
. .
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Scarts Processor
. .
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SAYEH educational processor
. .
|_
S80186
. .
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S1 Core
. .
|_
RV01 RISC-V core
. .
|_
rtf8088
. .
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RTF65002
. .
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RISE Microprocessor
. .
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RISC_Core_I
. .
|_
RISCOmpatible
. .
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RISC5x
. .
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risc16f84
. .
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RISC Microcontroller
. .
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Register Oriented Instruction Sets
. .
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Reduced AVR Core for CPLD
. .
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Raptor64
. .
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r2000 Soc
. .
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QUARK RISK
. .
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qrisc32 wishbone compatible risc core
. .
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PPX16 mcu
. .
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Potato Processor
. .
|_
plasma with FPU
. .
|_
Plasma - most MIPS I(TM) opcodes
. .
|_
Pepelatz MISC
. .
|_
PDP-8 Processor Core and System
. .
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PDP-11/70 CPU core and SoC
. .
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pAVR
. .
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P16C5x
. .
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OpenRISC 2000
. .
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OpenRisc 1200 HP, Hyper Pipelined OR1200 Core
. .
|_
OpenRISC 1000 (old)
. .
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OpenRISC 1000
. .
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openMSP430
. .
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OpenFire Processor Core
. .
|_
OpenCPU32
. .
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opencpu
. .
|_
OpenCores54x DSP
. .
|_
Open8 uRISC
. .
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OoOPs - Out-of-Order MIPS (TM) Processor
. .
|_
oks8
. .
|_
ODESS Multicore Project
. .
|_
NextZ80
. .
|_
Next 80186 processor
. .
|_
NEO430 Processor (MSP430-compatible)
. .
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nCore
. .
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Navré AVR clone (8-bit RISC)
. .
|_
Natalius 8 bit RISC
. .
|_
NanoBlaze: the expandable processor
. .
|_
myBlaze
. .
|_
MSP430 CPU core in VHDL
. .
|_
MPX 32-bit CPU
. .
|_
MMU for Z80 and eZ80
. .
|_
MIPS_enhanced
. .
|_
mipsr2000
. .
|_
mips789
. .
|_
MIPS32 Release 1 with support for FPU and other COPs
. .
|_
MIPS32 Release 1
. .
|_
Mips-FaultTolerant
. .
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mips compatible barrel processor
. .
|_
miniMIPS Superscalar
. .
|_
miniMIPS
. .
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Minimal PDP8/L implementation with 4K disk monitor system
. .
|_
Mini-Risc core
. .
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MicroSimplez
. .
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MicroRISC II
. .
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microprocessor za208
. .
|_
MCPU - A minimal CPU for a CPLD
. .
|_
MCIP open
. .
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McAdam's RISC Computer Architecture
. .
|_
MC6803/6801 CPU
. .
|_
MB-Lite
. .
|_
M65C02
. .
|_
M32632 32-bit Processor
. .
|_
M1 Core
. .
|_
LXP32, a lightweight 32-bit CPU core
. .
|_
LocationPU
. .
|_
Lightweight 8080 compatible core
. .
|_
Lightweight 8051 compatible CPU
. .
|_
Leros: A Tiny Microcontroller for FPGAs
. .
|_
Leros-32
. .
|_
LEM1_9
. .
|_
Lattice 6502
. .
|_
KLC32
. .
|_
K68
. .
|_
JOP: a Java Optimized Processor
. .
|_
Ion - MIPS(tm) compatible CPU
. .
|_
i8080 compatible processor using Am29XX bit slice family and microcoded design
. .
|_
i650
. .
|_
HyperMTA
. .
|_
HPC-16
. .
|_
HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core
. .
|_
HiCoVec - a configurable SIMD CPU
. .
|_
HF-RISC
. .
|_
HD63701 compatible core
. .
|_
HC11 Compatible - Gator uProcessor
. .
|_
GPU
. .
|_
FPz8
. .
|_
FORTH processor with Java compiler
. .
|_
Fluid Core (A Reconfigurable Pipelined RISC processor)
. .
|_
Featherweight RISC-V
. .
|_
erm16
. .
|_
ELM Embedded Processor
. .
|_
Educational RISC Processor
. .
|_
Educational 16-bit MIPS Processor
. .
|_
Edge Processor (MIPS)
. .
|_
ecpu_alu
. .
|_
Distributed limited cores
. .
|_
Diogenes: Student RISC System
. .
|_
Data Flow Processor
. .
|_
cpu65c02_tc - R65C02 Processor Soft Core with accurate timing
. .
|_
cpu6502_tc - R6502 Processor Soft Core with accurate timing
. .
|_
Cpu Generator
. .
|_
Cowgirl
. .
|_
copyBlaze
. .
|_
Confluence OpenRisc 1000
. .
|_
Codezero OpenRISC Port
. .
|_
Classic 5-Stage Pipeline MIPS
. .
|_
ClaiRISC - runs 12bit opcode PIC family.
. .
|_
CF State Space Processor
. .
|_
Brainfuck CPU
. .
|_
BiRiscV - 32-bit dual issue RISC-V CPU
. .
|_
AX8 mcu
. .
|_
AVRtinyX61core
. .
|_
AVR HP, Hyper Pipelined AVR Core
. .
|_
AVR Core
. .
|_
Attiny Atmega Xmega core
. .
|_
Atlas Processor Core
. .
|_
ASPIDA sync/async DLX Core
. .
|_
ARM4U
. .
|_
Aquarius
. .
|_
Apollo Guidance Computer NOR eMulator
. .
|_
aoR3000
. .
|_
ao68000 - Wishbone 68000 core
. .
|_
ao486
. .
|_
An inventory of soft processor cores
. .
|_
Amber ARM-compatible core
. .
|_
Alwcpu - A light weight CPU
. .
|_
alt_ISA
. .
|_
AltOr32 - Alternative Lightweight OpenRisc CPU
. .
|_
ag_6502 soft core with phase-level accuracy
. .
|_
aeMB
. .
|_
ae18
. .
|_
A-Z80 CPU
. .
|_
8080 Compatible CPU
. .
|_
8051 core
. .
|_
8-bit uP
. .
|_
8-bit Piepelined Processor
. .
|_
8-bit microcontroller with extended peripheral set
. .
|_
68hc08
. .
|_
68hc05
. .
|_
6809 and 6309 Compatible core
. .
|_
6502VHDL
. .
|_
4004 CPU and MCS-4 family chips
. .
|_
32 bit Processor
. .
|_
1664 microprocessor
. .
|_
16-bit Open uRISC core Processor
. .
|_
16-bit CPU based loosely on Caxton Foster's Blue architecture
. .
|_
16 Bit Microcontroller
.
|_
Library
. .
|_
Versatile library
. .
|_
TTL Library
. .
|_
Srdy-Drdy Library
. .
|_
Robot Control Library
. .
|_
Real-time Clock
. .
|_
ratpack
. .
|_
Random Number Generator Library
. .
|_
Qaztronic's libraries
. .
|_
openVeriFLA - FPGA logic analyzer
. .
|_
MyGPU
. .
|_
Library of functions using/for DP streaming interface
. .
|_
Library of commonly used components
. .
|_
Library of common functions
. .
|_
Library of basic components with/for DP streaming interface
. .
|_
HDL-deflate
. .
|_
gh vhdl library
. .
|_
Funbase IP library
. .
|_
fixed_extensions
. .
|_
extension_pack
. .
|_
Common Design Environment
.
|_
ECC core
. .
|_
Yet Another Hamming Encoder and Decoder
. .
|_
Viterbi Decoder (AXI4-Stream compliant)
. .
|_
Ultimate CRC
. .
|_
Turbo Decoder
. .
|_
Spread Spectrum modulator and demodulator using BPSK
. .
|_
RS_5_3_GF256
. .
|_
Reed-Solomon Decoder/Encoder
. .
|_
Reed-Solomon Decoder (31, 19, 6)
. .
|_
Reed-Solomon Codec Generator
. .
|_
Reed Solomon Encoder/Decoder
. .
|_
Reed Solomon Encoder
. .
|_
Reed Solomon Decoder (204,188)
. .
|_
Reed Solomon (9,5) Encoder/Decoder
. .
|_
Product Code Iterative Decoder
. .
|_
PCI Express 16 bit CRC verilog file
. .
|_
ham_7_4_enc
. .
|_
Double error correcting (DEC) BCH encoder / decoder
. .
|_
Constellation Encoder
. .
|_
Configurable Hamming Generator
. .
|_
Configurable BCH Encoder and Decoder
. .
|_
CF LDPC Decoder
. .
|_
802.3an LDPC Encoder
. .
|_
802.3an LDPC Decoder
.
|_
DSP core
. .
|_
Wideband FFT
. .
|_
VIIRF - Versatile IIR Filter
. .
|_
Radix-2 SDF FFT
. .
|_
Quadrature Oscillator
. .
|_
Polyphase Decimation Filter
. .
|_
Pipelined fixed point elementary functions (div, sin, cos, exp, atan2, sqrt)
. .
|_
Pipelined FFT/IFFT 64 points processor
. .
|_
Pipelined FFT/IFFT 256 points processor
. .
|_
Pipelined FFT/IFFT 128 points processor
. .
|_
Pipelined DCT/IDCT
. .
|_
PID controller
. .
|_
NCO / Periodic Waveform Generator
. .
|_
Low-Pass IIR Filter
. .
|_
low-pass filter FIR
. .
|_
Low Power FIR Filter
. .
|_
IQ Phase and Gain Correction
. .
|_
IMA ADPCM Encdoer & Decoder
. .
|_
IIR
. .
|_
Hilbert Transformer
. .
|_
Generic FIR Filter
. .
|_
Generic FIR filter
. .
|_
G-FIR TF/DF
. .
|_
Floating-point FFT/IFFT
. .
|_
FirGen/MultGen
. .
|_
filtro_FIR
. .
|_
FFT-based FIR Filter
. .
|_
Fast Hadamhard Transforms
. .
|_
Dynamic resizable streaming the base 2 FFT
. .
|_
DSP WishBone Compatible Cores
. .
|_
Double Clocked FFT Core
. .
|_
DDS Synthesizer
. .
|_
Correlation statistics core
. .
|_
Configurable High Speed Viterbi Decoder
. .
|_
CIC-filter core
. .
|_
CIC filter
. .
|_
CIC Decimation Filter
. .
|_
CF FIR Filter
. .
|_
Cascaded FIR Filter
. .
|_
Canny Edge Detector
. .
|_
Biquad IIR Filter Core
. .
|_
all-pole IIR filters
. .
|_
Adaptive LMS equalizer
. .
|_
A Linked List Run-Length-Based Single-Pass Connected Component Analysis
.
|_
Crypto core
. .
|_
XTEA Crypto Core
. .
|_
XTEA Core
. .
|_
Twofish Core
. .
|_
twofish 128/192/256
. .
|_
Tiny Encryption Algorithm
. .
|_
The Grain stream cipher
. .
|_
SystemC/Verilog MD5
. .
|_
SystemC/Verilog DES
. .
|_
Simple to use SHA-2 algorithm
. .
|_
Simple Camellia Crypto Core
. .
|_
Simon Core
. .
|_
SHA3 (KECCAK)
. .
|_
SHA256 HASH CORE
. .
|_
SHA1 Secure Hash Algorithm
. .
|_
SHA-256 Core
. .
|_
SHA cores
. .
|_
Secure Hash Standard 256 bits
. .
|_
Salsa20StreamCipher
. .
|_
RTEA 128/256
. .
|_
RSA Processor
. .
|_
RSA
. .
|_
rc6 cryptography
. .
|_
RC4 Pseudo-random stream generator
. .
|_
Present Cipher Encryption Core
. .
|_
Present - a lightweight block cipher
. .
|_
Pipelined AES
. .
|_
Nugroho Free Hash Cores
. .
|_
Nugroho Free Crypto Cores
. .
|_
NOEKEON Core (lightweight block cipher)
. .
|_
Montgomery modular multiplier and exponentiator
. .
|_
Mini AES
. .
|_
MD5 Pipelined
. .
|_
IOTA PoW Pearl-Diver Curl-P81
. .
|_
IDEA core
. .
|_
HIGHT Crypto Core
. .
|_
high throughput and low area aes core
. .
|_
High Radix Montgomery RSA Crypto Core
. .
|_
Hardware implementation of SHA-3 (keccak) algorithm
. .
|_
gost28147-89
. .
|_
GOST 28147-89
. .
|_
Galois Counter Mode Advanced Encryption Standard GCM-AES
. .
|_
Flexible Design of a Modular Simultaneous Exponentiation Core
. .
|_
fast AES-128 Encryption only cores
. .
|_
DESX Core
. .
|_
DESLX Core
. .
|_
DESL Core
. .
|_
DES/Triple DES IP Cores
. .
|_
DES Core
. .
|_
csa
. .
|_
Crypto-PAn
. .
|_
Compact CLEFIA for FPGA
. .
|_
Chip-to-chip authentication with PUF and RSA
. .
|_
Camellia cores
. .
|_
BTCMiner - Open Source Bitcoin Miner
. .
|_
Bluespec MD6
. .
|_
Bluespec Cryptosorter
. .
|_
Bitcoin Double SHA256
. .
|_
Basic RSA Encryption Engine
. .
|_
Basic DES Crypto Core
. .
|_
B-163 EC Arithmetic
. .
|_
Avalon AES ECB-Core (128, 192, 256 Bit)
. .
|_
AES128
. .
|_
AES-VHDL
. .
|_
AES-128 Encryption
. .
|_
AES SystemVerilog behavioral model
. .
|_
AES encryption all keylength
. .
|_
AES decryption IP (128 bit)
. .
|_
AES Decryption Core for FPGA
. .
|_
AES cores (compact)
. .
|_
AES core modules
. .
|_
AES-1
. .
|_
AES
. .
|_
3DES (Triple DES) / DES (VHDL)
. .
|_
128/192 AES
. .
|_
AES (Rijndael) IP Core
.
|_
Coprocessor
. .
|_
xgate
. .
|_
ORSoC Graphics Accelerator
. .
|_
JT51 - YM2151 compatible core
. .
|_
Floating Point Unit
. .
|_
CPU Code Execution Timestamp
. .
|_
CF Reconfigurable Computing Array
.
|_
Communication controller
. .
|_
YANU - UART with predictive interrupt events on Rx/Tx buffers state
. .
|_
xSPi
. .
|_
WishboneAXI
. .
|_
wishbone uart controller 8 bit
. .
|_
Wishbone SD Card Controller
. .
|_
Wishbone Register Bank Intercon Multi-master Multi-slave
. .
|_
Wishbone protocol to axi4 protocol
. .
|_
Wishbone LPC Host and Peripheral Bridge
. .
|_
Wiegand Controller (SIA AC-01-1996.10)
. .
|_
wb_uart
. .
|_
vSPI
. .
|_
Versatile IO
. .
|_
USB to UART
. .
|_
USB Host Core
. .
|_
USB FT232H Avalon-MM interface
. .
|_
USB Device Core
. .
|_
USB 2.0 Function Core
. .
|_
USB 1.1 PHY
. .
|_
USB 1.1 Host and Function IP core
. .
|_
USB 1.1 Function IP Core
. .
|_
USB 1.1 Simulation (VHDL)
. .
|_
USB 1.1 PHY (VHDL)
. .
|_
ULPI Wrapper
. .
|_
UDP/IPv4 for 10G Ethernet
. .
|_
UDP/IP Core
. .
|_
UART8SYSTEMC
. .
|_
uart6551
. .
|_
UART16750
. .
|_
UART with PLB interface
. .
|_
UART To SPI
. .
|_
UART to Bus
. .
|_
UART to / from fiber optic
. .
|_
Uart block
. .
|_
UART 16550 core
. .
|_
Uart (FIFO cpu interface) with SV Self-Checking Testbench
. .
|_
tiny SPI
. .
|_
TIME SLOT INTERCHANGE DIGITAL SWITCH
. .
|_
TI TLV320AIC1106 PCM Codec Altera Avalon IP core
. .
|_
TDM controller
. .
|_
TCP/IP socket
. .
|_
TCP IP Core
. .
|_
SystemVerilog uart16550
. .
|_
SystemC USB1.1 IP Core
. .
|_
Super-I/O (SIO) controller
. .
|_
Stepper Motor Controller
. .
|_
SSP_UART
. .
|_
SSP_Slv
. .
|_
SPORT Interface
. .
|_
SPIxIF
. .
|_
spislave
. .
|_
spigpio
. .
|_
SPI-slave Wishbone-Master
. .
|_
SPI Verilog Master & Slave modules
. .
|_
SPI serial DAC interface
. .
|_
SPI Master/Slave Interface
. .
|_
spi master receiver for ADC (AD747x)
. .
|_
SPI Master Lightweight
. .
|_
SPI Flash controller
. .
|_
SPI core
. .
|_
SPI Controller for AD/DA chips on S3E/A/AN Starter Kits
. .
|_
SPI controller core
. .
|_
SPI based SD card controller
. .
|_
SPDIF Transmitter
. .
|_
SPDIF Interface
. .
|_
SpaceWireSystemC
. .
|_
SpaceWire Light
. .
|_
SpaceWire
. .
|_
smbus_if
. .
|_
Smartcard interface (ISO7816-3)
. .
|_
Small 1-wire (onewire) master, with Altera tools integration
. .
|_
Single Slot PCM Interface
. .
|_
Simple UART for FPGA
. .
|_
Simple RS232 UART
. .
|_
Simple Asynchronous Serial Controller
. .
|_
Simple AES3 / SPDIF receiver
. .
|_
SGMII
. .
|_
Serializer / Deserializer for audio fiber optic
. .
|_
Serial Uart
. .
|_
Serial UART
. .
|_
Serial to parallel converter
. .
|_
Serial ATA Host Bus Adapter Core for Virtex 6
. .
|_
SDRAM AXI4
. .
|_
SDHC Self Configuring Core
. .
|_
SD/MMC Controller
. .
|_
SD/MMC Bootloader
. .
|_
SD/eMMC/MMC card emulator
. .
|_
sd card controller
. .
|_
Scan Based Serial Communication
. .
|_
Saturn
. .
|_
SATA PHY
. .
|_
SATA Controller
. .
|_
SATA 2 HOST Controller
. .
|_
RXAUI Interface and XAUI to RXAUI Interface Adapter
. .
|_
rtfSimpleUart
. .
|_
RS232
. .
|_
RS232
. .
|_
RapidIO IP library
. .
|_
Quadrature Decoder / Counter
. .
|_
Quad SPI Flash Controller
. .
|_
PS2 Core
. .
|_
PS/2 Host Controller
. .
|_
PLB-to-WB Bridge
. .
|_
Playstation 2 network adaptor IC CXD9731
. .
|_
Pipelined wishbone to AXI converter
. .
|_
PC-FPGA Communication Platform
. .
|_
opb_usblite
. .
|_
OPB-compatible OneWire Master
. .
|_
OPB SPI Slave
. .
|_
OP2P (OpenPeerToPeer Interface)
. .
|_
One Wire Master
. .
|_
OHCI Full/Low-Speed USB Host Controller
. .
|_
OFDM modem
. .
|_
neopixel ws2812
. .
|_
nec ir remote control decoder
. .
|_
Multimicrophone Interface
. .
|_
Minimal UART Core
. .
|_
Minimac - the minimalist Ethernet MAC
. .
|_
Manchester UART
. .
|_
Manchester to UART converter
. .
|_
Manchester Decoder for Wireless
. .
|_
MADI Receiver
. .
|_
lzs
. .
|_
LPC ROM emulator on USB dongle FPGA core set
. .
|_
JTAG Slave / BoundaryScan Slave
. .
|_
JTAG Master
. .
|_
Iso7816_3_Master
. .
|_
IrDA
. .
|_
IPv4 Ethernet Packet Creator and Transmitter
. .
|_
IEEE 802.15.4 CRC
. .
|_
IEEE 802.15.4 Core (physical layer)
. .
|_
i8255 realisation in Verilog
. .
|_
I2S to WishBone
. .
|_
I2S to Parallel Interface
. .
|_
I2S to Paralell ADC/DAC controller
. .
|_
I2S Interface
. .
|_
i2c_to_wb
. .
|_
i2cgpio
. .
|_
I2C Traffic Logger
. .
|_
I2C Slave
. .
|_
I2C Repeater
. .
|_
I2C Multiple Bus Controller
. .
|_
I2C master/slave Core
. .
|_
I2C Master Slave Core
. .
|_
I2C controller core
. .
|_
HyperTransport Tunnel
. .
|_
HDLC controller
. .
|_
HDB3/B3ZS Encoder+Decoder
. .
|_
Hardware Assisted IEEE 1588 IP Core
. .
|_
GPIB (IEEE-488) controller
. .
|_
General-Purpose I/O (GPIO) Core
. .
|_
Gamepads
. .
|_
FTDI Async FIFO I/F to Wishbone Bridge
. .
|_
FT245R interface
. .
|_
FT2232H USB Avalon Core
. .
|_
FPGA remote slow control via UART 16550
. .
|_
FPGA Communication Framework
. .
|_
FireWire (IEEE 1394)
. .
|_
Fade - Light L3 Ethernet protocol for transmission of data from FPGA to embedded PC
. .
|_
EZUSB communication core
. .
|_
Ethernet Switch on Configurable Logic
. .
|_
Ethernet SMII
. .
|_
Ethernet MAC 10/100 Mbps
. .
|_
Ethernet 10GE MAC
. .
|_
Ethernet 10GE Low Latency MAC
. .
|_
Ethernet 100/1000 Mbps
. .
|_
Etherblade.net - FPGA ethernet line-rate encapsulator (EoIP, EoMPLS, PBB etc)
. .
|_
EPP v1.9
. .
|_
EBU/spdif to I2S project
. .
|_
E1-G.703,G.704,G.706 framer/deframer
. .
|_
E1 Framer/Deframer
. .
|_
DQPSK Mapper
. .
|_
Documented Verilog UART
. .
|_
DMX512 transceiver
. .
|_
DMT Transceiver
. .
|_
Core1990: Interlaken protocol
. .
|_
Cheap Ethernet interface
. .
|_
CAN Protocol Controller
. .
|_
Bluetooth baseband controller
. .
|_
Bluespec 802.11a Transmitter
. .
|_
Bitwise addressable GPIO
. .
|_
baud generator
. .
|_
Automatic BAUD rate generator
. .
|_
Asynchronous SPI master
. .
|_
Async 8b/10b enc/dec
. .
|_
ARINC 429 Transmitter and Receiver
. .
|_
APB to SPI
. .
|_
APB to I2C
. .
|_
Another Wishbone Controlled UART
. .
|_
Another SPI Controller (with FIFO)
. .
|_
AMI / HDB1 Line Codes
. .
|_
ahci
. .
|_
adat receiver
. .
|_
A VHDL CAN Protocol Controller
. .
|_
a VHDL 16550 UART core
. .
|_
8b10b Encoder/Decoder
. .
|_
1G Ethernet DPI
. .
|_
1G Ethernet ARP
. .
|_
1G eth UDP / IP Stack
. .
|_
16 Quadrature Amplitude Modulator and Demodulator
. .
|_
10_100_1000 Mbps tri-mode ethernet MAC
. .
|_
10G Ethernet MAC
. .
|_
1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)
. .
|_
100 MB/s Ethernet MAC Layer Switch
. .
|_
10/100M Ethernet-FIFO convertor
.
|_
Prototype board
. .
|_
ZTEX USB-FPGA Module 2.14
. .
|_
ZTEX USB-FPGA Module 2.13
. .
|_
ZTEX USB-FPGA Module 2.04
. .
|_
XENIE programmable 10GBASE-T FPGA module
. .
|_
USB-FPGA Module 2.16
. .
|_
USB-FPGA Module 1.15
. .
|_
USB FPGA MODULE 1.2
. .
|_
USB FPGA Module 1.11
. .
|_
Technologic Systems TS-7300 FPGA Computer
. .
|_
Spartan 6 PCIexpress card
. .
|_
Spartan 6 + PIC32 + USB + Ethernet
. .
|_
Raggedstone PCI Spartan-3 board
. .
|_
Plataforma de Hardware Reconfigurable
. .
|_
PCI card with Xilinx X3CS500E
. .
|_
PCI Board
. .
|_
OpenRisc Development Board
. .
|_
OPENCORES Application Board 1 (OAB1)
. .
|_
Open Design Prototype Board
. .
|_
OMRP Prototype board v2
. .
|_
OCRP-2 board
. .
|_
OCRP-1 board
. .
|_
Milkymist One interactive VJ station
. .
|_
Micro FPGA Board
. .
|_
MAXII-Evalboard
. .
|_
LPC ROM, SPI ROM, 8bit ROM emulator on Artec Dongle II board
. .
|_
Linux & Xilinx FPGA Dev Board
. .
|_
kiss-board
. .
|_
Internal Logic State Analyzer
. .
|_
IIE-PCI Board
. .
|_
IGOR - A microprogrammed LISP machine
. .
|_
Griva Basic board
. .
|_
Game-Trees FPGA implementation (Othello Game)
. .
|_
EUS FS - Alice II - Embeddable Single Board Computer
. .
|_
EtraxFS & Xilinx FPGA dev board with building blocks
. .
|_
EP2C35 Board
. .
|_
de1_olpcl2294_system
. .
|_
Butterfly Light
. .
|_
Audio DSP PCI Card
. .
|_
arduFPGA iCE40UP5K
. .
|_
aes220 High-Speed USB FPGA mini-module
. .
|_
ACEX 1K50 board
.
|_
Arithmetic core
. .
|_
[128bit] Pseudo Random Number Generator Using Linear-feedback Shift Registers
. .
|_
YAC - Yet Another CORDIC Core
. .
|_
Xilinx Virtex FLoating Point
. .
|_
VIterbi_Tx_Rx
. .
|_
Viterbi HDL Code Generator
. .
|_
Versatile counter
. .
|_
Unsigned serial divider
. .
|_
Universal multi-function CORDIC
. .
|_
True matrix 3x3 multiplier
. .
|_
trigonometric functions (degrees) in double fpu
. .
|_
Tiny Tate Bilinear Pairing
. .
|_
Ternary (3-input) Adder
. .
|_
Tate Bilinear Pairing
. .
|_
Tanh Approximation Custom Instruction for NIOS II
. .
|_
suslik scalar risc cpu
. .
|_
Superscalar Version Of DLX
. .
|_
Single Clock Unsigned Division Algorithm
. .
|_
Single 14 Segment Display Driver with Limited ASCII Decoder
. .
|_
SineAndCosineTable
. .
|_
Signed integer divider
. .
|_
Signed / unsigned multiplier and divider with prime number generator as test circuit
. .
|_
Requantizer
. .
|_
Reed-Solomon Decoder
. .
|_
Reconfigurable Hardware Platform
. .
|_
Ray Tracing Arithmetic Engine
. .
|_
radix 4 complex fft
. .
|_
QuadFixedPoint32 Arithmetic Unit
. .
|_
PYRAMID Integer Multiplier unit
. .
|_
Priority Encoder
. .
|_
Population Counter Generator
. .
|_
pipeline mips in vhdl
. .
|_
PID Controler
. .
|_
Parametrized FFT engine
. .
|_
Parameterizable integer square root by the digit-by-digit method
. .
|_
Parameterizable adder tree
. .
|_
openFPU64
. .
|_
Numbert sort device O(N)
. .
|_
Non Linear Pseudo Random Generator
. .
|_
Multiply-Accumulate Operation (MAC)
. .
|_
Multiplier library
. .
|_
Model of hybrid classical-quantum computing method
. .
|_
MODBUS Implementation in VHDL
. .
|_
mod3_calc
. .
|_
MESI Coherency InterSection Controller
. .
|_
Maximum/Minimum binary tree finder
. .
|_
LZRW1 Compressor Core
. .
|_
Logarithm function, base-2, single-cycle
. .
|_
LFSR-Random number generator
. .
|_
LCD162B Behavior Model
. .
|_
Huffman Decoder
. .
|_
HIERARCHICAL Integer Multiplier unit
. .
|_
Heap sorter for FPGA
. .
|_
HCSA adder and Generic ALU based on HCSA
. .
|_
Hardware Load Balancer for Multi-Stage Software Router
. .
|_
Hardware implementation of Binary Fully Digital Phase Locked Loop
. .
|_
Hardware Division Units
. .
|_
GNExtrapolator
. .
|_
Generic LFSR Generator
. .
|_
Generic Galois LFSR
. .
|_
Generic Booth Multiplier
. .
|_
Gaussian Noise Generator
. .
|_
FT816Float - Floating point accelerator
. .
|_
FPU Double VHDL
. .
|_
FPU
. .
|_
FPGA-based Median Filter
. .
|_
Floating-Point Logarithm Unit
. .
|_
Floating Point Adder and Multiplier
. .
|_
Fixed-point quadratic polynomial
. .
|_
Fixed Point Square Root (Recursive Algorithm)
. .
|_
Fixed Point Math Library for Verilog
. .
|_
Fixed Point Arithmetic Modules
. .
|_
Elliptic Curve Group
. .
|_
DVB-S2 LDPC Decoder
. .
|_
double_fpu_verilog
. .
|_
Discrete Cosine Transform core
. .
|_
DCT - Discrete Cosine Transformer
. .
|_
cr_div - Cached Reciprocal Divider
. .
|_
CRCAHB
. .
|_
CORDIC core
. .
|_
CORDIC arctangent for IQ signals
. .
|_
Configurable Parallel Scrambler
. .
|_
configurable CRC core
. .
|_
configurable cordic core in verilog
. .
|_
Complex Operations ISE for NIOS II
. .
|_
Complex Multiplier
. .
|_
Complex Gaussian Pseudo-random Number Generator
. .
|_
Complex Arithmetic Operations
. .
|_
CF Floating Point Multiplier
. .
|_
CF FFT
. .
|_
CF Cordic
. .
|_
Cellular Automata PRNG
. .
|_
cavlc decoder
. .
|_
Booth Array Multiplier
. .
|_
Bluespec SystemVerilog Reed Solomon Decoder
. .
|_
Binary to BCD conversions, with LED display driver
. .
|_
BCD adder
. .
|_
Anti-Logarithm (square-root), base-2, single-cycle
. .
|_
ANN
. .
|_
AES128
. .
|_
Adder library
. .
|_
8 bit Vedic Multiplier
. .
|_
5x4Gbps CRC generator designed with standard cells
. .
|_
4-bit system
. .
|_
2D FHT
. .
|_
1 bit adpcm codec
.
|_
Memory core
. .
|_
ZBT SRAM Controller
. .
|_
Wishbone Interface for SPI FLASH
. .
|_
Wishbone FLASH Interface for Parallel FLASH
. .
|_
Wishbone DDR3 SDRAM Controller
. .
|_
wb_size_bridge
. .
|_
wb_async_mem_bridge
. .
|_
Versatile memory controller
. .
|_
Versatile FIFO
. .
|_
USB NAND Flash Reader
. .
|_
synchronous_reset_fifo with testbench
. .
|_
Stack design
. .
|_
SSRAM interface
. .
|_
srl_fifo
. .
|_
sp_ram to 3p_ram WISHBONE Wrapper
. .
|_
Single Port ASRAM
. .
|_
Scratch DDR SDRAM Controller
. .
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RAM_wb
. .
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RAM library
. .
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Parametrized FIFO based on SRL16E
. .
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openHMC
. .
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Open FreeList
. .
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OPB PSRAM Controller
. .
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NAND Controller (ONFI compliant)
. .
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Memory sizer
. .
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Memory cores
. .
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High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline
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High Performance Dynamic Memory Controller
. .
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High Latency Bursting WISHBONE Wrapper for Xilinx MIG
. .
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Generic FIFOs
. .
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Generic FIFO
. .
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Functional simulation models for commercially available RAMs
. .
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FIFO library
. .
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FAT32 Parser
. .
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DPSFmnCE
. .
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DirectMappedCacheController
. .
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DDR3 Synthesizable BFM
. .
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DDR2 SDRAM Controller
. .
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DDR2 mem controller for Digilent Genesys Board
. .
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DDR2
. .
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DR SDRAM Controller Core
. .
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CFI flash controller
. .
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CF Interleaver
. .
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BRSFmnCE
. .
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Asynchronous WISHBONE-compatible SDRAM controller
. .
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2Q cache
. . .
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8/16/32 bit SDRAM Controller
. .
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16-bit SDRAM Controller
. .
|_
DDR3 SDRAM controller
Thư Viện Đề Tài Luận Văn - Đồ Án
Thư Viện Hệ Thống Nhúng - Embeded System Books
Thư Viện Kỹ Thuật Số - Digital Technical Books
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Máy Biến Trạng Thái - State Machine Design Books
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Kỹ Thuật Số Cơ Bản - Basic Digital Technical Books
Thư Viện VIP Model - Verification IP (VIP) Directory
Thư viện về FPGA-CPLD - FPGA & CPLD Specifications
Tài liệu DFT -Design For Test and Tools User Guide
Tài liệu về CMOS - CMOS Structure Documents
Tài Liệu Ngôn Ngữ Script Linux (cshell, bash shell, perl script language)
Thư Viện Bài Tập Semicon
Tài Liệu Xây Dựng Môi Trường - Verification Simulation Books
Tài Liệu System Verilog - System verilog Books
Thư Viện Về Phần Mềm trong Thiết Kế Vi Mạch - Tools Usage Guide in IC design
Tài Liệu STA - Static Timing Analysis Books
Tổng Hợp Tần Sồ - Logic Synthesis & Tool Guide Books
Tài Liệu Verilog, VHDL HDL - Verilog & VHDL Books
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Tài Liệu VHDL - VHDL Language Books
.
|_
Verilog HDL Books
Tài Liệu Thiết Kế SOC - SOC (System on Chip) Design Books
Tài Liệu Thiết Kế ASIC - ASIC design Books
Tài Liệu Thiết Kế Vi Mạch - IC Design Reference Books
Bài Học Vi Mạch Hay - Good Lectures from Educational Courses
Thư Viện Thiết Kế Mẫu Tham Khảo - Example Design for Study
CPU Core + IPs core + Full chip Specifications
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Bus Specifications
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OpenCore Bus Architecture Specification
. .
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Bus Bridge (arbiter) Specification
. .
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Synopsys Bus Architecture Specification
. .
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IBM Bus Architecture Specification
. .
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Intel Bus Architecture Specification
. .
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Hitachi Bus Architecture Specification
. .
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ARM Bus Architecture Specifications
.
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SOC Specifications
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IP Core Specifications
. .
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I2S Specifications
. .
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Interrupt Controller Specifications
. .
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SRAM Controller Specifications
. .
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SDHC Controller Specifications
. .
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TDM Specifications
. .
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RTC (Real Time Clock) Specifications
. .
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DMA Controller Specifications
. .
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IrDA Specifications
. .
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SPI Specifications
. .
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I2C Specifications
. .
|_
UART Specifications
. .
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SATA Controller Specifications
. .
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Watchdog Timer (WDT) Specifications
. .
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Security Specifications
. .
|_
Cache Controller Specifications
. .
|_
Serial Flash Controller Specifications
. .
|_
NOR Flash Controller Specifications
. .
|_
NAND FLASH Controller Specifications
. .
|_
SRAM Controller Specifications
. .
|_
On Chip Memory Specifications
. .
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SRAM Controller Specifications
. .
|_
DDR Controller Specifications
. .
|_
Bluetooth Specifications
. .
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USB 1.0 Specifications
. .
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PCIE Specifications
. .
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SCI Specifications
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PWM Specifications
. .
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Ethernet Specifications
. .
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USB PHY Specifications
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PCI Specifications
. .
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USB 2.0 Specification
.
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CPU Core Specifications
. .
|_
Open Core Specifications
. .
|_
Hitachi Core Specifications
. .
|_
Intel Core Specifications
. .
|_
IBM Core Specifications
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|_
ARM Core Specifications
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