Trung tâm đào tạo thiết kế vi mạch Semicon
Login
Username:
Password:
Forgot your password?
Forgot your username?
ĐĂNG KÝ TÀI KHOẢN ĐỂ TRUY CẬP NHIỀU TÀI LIỆU HƠN!
Create an account
Name:
*
Username:
*
Email:
*
Password:
*
Verify Password:
*
Fields marked with an asterisk (*) are required.
Create an account
Skip to content
HOME
CORPORATE
About Semicon
Management Team
Partnership
OFFERINGS
Verification
Digital Verification
Software
Training
Course Registration
Basic IC Design Course
Intermediate Design Course
High-class IC Design Course
SystemVerilog Course
VHDL Language Course
Physical Design
Embedded System
IP Design Development
IC News
Vietnamese IC News
Technology IC Product News
IC Lectures
ASIC Lectures
IC Video Lectures
Careers
Soft Skill Experiences
ASIC Jobs
IT Jobs
Contact Us
DOWNLOAD
Downloads Home
Search Document
Search a Document
Search Keyword
:
Select Category
:
All Categories
Tài Liệu Luyện GRE
Tài Liệu Luyện IELTS
Hội Thảo Thiết Kế Vi Mạch
Thư Viện Sơ Đồ Khối IP - IP Block Diagram Library
Sample Projects Download
.
|_
Uncategorized
. .
|_
x86 Compatible SOC with Video , keyboard , GPIO , uart
. .
|_
X.25 interface core
. .
|_
wishbone_checker
. .
|_
Wishbone to NPI core
. .
|_
VoIP Smart IP Phone SI-160
. .
|_
Viterbi Decoder (K=7, G=(171, 133))
. .
|_
Viterbi Decoder
. .
|_
Viterbi Decoder
. .
|_
VHDL wavefile package
. .
|_
VHDL MD5 Hash Core (Complete)
. .
|_
Verilog Rijndael (AES) Implementation
. .
|_
Verilator Verilog to C++/SystemC compiler
. .
|_
ultravec
. .
|_
Trapezoidal Shaper
. .
|_
transmitter
. .
|_
tindy lattic fpga project for dlp
. .
|_
thocon
. .
|_
SystemC CORDIC
. .
|_
svmac
. .
|_
Subtractive / Additive Synthesizer
. .
|_
STS-1 soft core
. .
|_
SPORT Interface implementation in VHDL for Winbond Micro controller
. .
|_
SPI-Slave
. .
|_
smallARM
. .
|_
slave vme bridge
. .
|_
Single cycle multiply accumulate block
. .
|_
simpleUart -
. .
|_
Simple Interruput Controller Core
. .
|_
serpent_core
. .
|_
SEAnb
. .
|_
sdram_ctrl
. .
|_
sdram control core
. .
|_
SDR SDRAM Controller
. .
|_
SCSI Interface
. .
|_
RISC CPU (DLX) in SystemC
. .
|_
rc5
. .
|_
RadioHDL
. .
|_
Programmable DCT Accelarator with 16 bit Microcontroller
. .
|_
Profibus
. .
|_
pnctl
. .
|_
Pipelined 8-point DCT
. .
|_
Performance counter for Microblaze
. .
|_
PCI to IDE Controller core
. .
|_
Packet Filter
. .
|_
OpenTech Cd-rom
. .
|_
openCPU 67-80-85
. .
|_
open 1394 intellectual property
. .
|_
OPB-compatible UDP transceiver
. .
|_
OPB-compatible PS/2 Keyboard Controller
. .
|_
Omega CPU - Alpha like clone
. .
|_
ocmips
. .
|_
ntsc video encoder
. .
|_
NorthBridge (PPC)
. .
|_
nonrestoringsquareroot
. .
|_
ngocminh
. .
|_
NeoT
. .
|_
Multiplierless 64 point FFT Processor
. .
|_
MPEG-4 Video Coding
. .
|_
mips single cycle microprocessor
. .
|_
Mini-ACEX1K
. .
|_
mil std 1553b
. .
|_
MD5 Hash Core RFC 1321
. .
|_
mcu
. .
|_
Matrix Determinant Processor
. .
|_
Manchester Encoder / Decoder
. .
|_
Macroblock Motion Detection
. .
|_
LWMIPS
. .
|_
LPC(Low Pin Count) controller and peripherals
. .
|_
Light Uart
. .
|_
ldpc
. .
|_
KCPSM3 Maskable Interrupt
. .
|_
JPEG Decoder
. .
|_
intel 8031
. .
|_
I2C slave for data transfer
. .
|_
High speed adder for large bit size computation
. .
|_
GCPU
. .
|_
Function Generator
. .
|_
FSL 2 Serial Peripheral
. .
|_
FPGA Based PWM Inverter
. .
|_
Floppy Drive Controller
. .
|_
Floating Point Square Root
. .
|_
floating point adder/subtractor
. .
|_
Fix-Point Cordic Engine
. .
|_
FIR-Gen
. .
|_
fft_32
. .
|_
FastAES
. .
|_
eMotion NEMO Implementation
. .
|_
Dallas one-wire protocol with a DS1821 top level demo
. .
|_
CLAW: A two way multithreaded (8 threads) VLIW Processor
. .
|_
Cereon
. .
|_
BRISC microprocessor
. .
|_
ALU with selectable inputs and outputs
. .
|_
AHB ARBITER
. .
|_
AC97 Controller
.
|_
Video controller
. .
|_
Yet Another VGA
. .
|_
Yet another verilog VGA
. .
|_
Wishbone Monitor Controller
. .
|_
Wire-Frame 3D Graphics Accelerator IP Core
. .
|_
Video Stream Scaler
. .
|_
Video Starter Kit
. .
|_
Video Dithering
. .
|_
Video compression systems
. .
|_
VGA/LCD Controller
. .
|_
ULA chip for ZX Spectrum
. .
|_
tft lcd controller
. .
|_
Sharp LQ057Q3DC02 LCD Controller
. .
|_
Sharp LQ057Q3DC02 LCD Controller
. .
|_
rtfTextController
. .
|_
rtfSpriteController / Hardware cursors
. .
|_
rtfBitmapController
. .
|_
ROSETTA Configurable Dot Matrix Display Controller
. .
|_
PAL/NTSC encoder
. .
|_
OV7670 Camera Video Capturing
. .
|_
openGFX430
. .
|_
OPB-compatible VGA character display, no DAC
. .
|_
NPI graphics controller
. .
|_
MPEG2 Video decoder
. .
|_
Motion Estimation Processor
. .
|_
Monochrome Text-Mode VGA Video Display Adapter
. .
|_
MiniGA - High Quality PAL Encoder
. .
|_
Memory mapped LCD Controller (KS0073)
. .
|_
LCD to HDMI output IP
. .
|_
LCD Driver
. .
|_
JPEG Hardware Compressor
. .
|_
JPEG Encoder Verilog
. .
|_
JPEG Encoder
. .
|_
JPEG codec library based on microblaze
. .
|_
Image warping/Texture mapping core
. .
|_
H.264/AVC Baseline Decoder
. .
|_
Graphics Accelerator
. .
|_
Graphical LCD interfaces
. .
|_
FlexGripPlus General Purpose Graphics Processing Unit (GPGPU) core
. .
|_
FastMemoryLink VGA framebuffer controller
. .
|_
Demosaic (Bilinear)
. .
|_
Color Converter
. .
|_
CCITT-G4(tiff) compression
. .
|_
Bluespec H.264 Decoder
. .
|_
axi_vga
. .
|_
AXI4 to VGA Frame Buffer with Linux driver
. .
|_
16x2_lcd_display
. .
|_
(M)JPEG Decoder
.
|_
Testing / Verification
. .
|_
Wishbone Scope
. .
|_
Video Pattern Generator
. .
|_
VHDL Whisbone Test Bench
. .
|_
Uart2BusTestBench
. .
|_
UART observer
. .
|_
The VHDL Test Bench
. .
|_
SystemVerilog Directed Test Bench
. .
|_
StaplPlayer
. .
|_
Soundfile Testbench
. .
|_
socgen
. .
|_
SocExplorer
. .
|_
Simulation tools library
. .
|_
PRBS Signal Generator and Checker
. .
|_
PlTbUtils
. .
|_
Open JTAG project
. .
|_
LogicProbe
. .
|_
i2clcd
. .
|_
High Load configurable test project
. .
|_
HASM TestBench Vector Generator
. .
|_
Generic AXI slave stub
. .
|_
Generic AXI master stub
. .
|_
Generic APB slave stub
. .
|_
Generic APB master stub
. .
|_
Generic AHB slave stub
. .
|_
Generic AHB master stub
. .
|_
FROM and TO files
. .
|_
FPO (Logic Analyzer)
. .
|_
EziDebug
. .
|_
DS1621 model
. .
|_
Diagnostics library
. .
|_
Constrained random test generator
. .
|_
c - VHDL Co-Simulation with FLI
. .
|_
Bus Transaction Monitor with JTAG
. .
|_
Boost Converter
.
|_
System controller
. .
|_
Wupper: PCIe DMA Engine for Xilinx FPGAs
. .
|_
WB LCD Character Display Controller
. .
|_
TI DSP and Xilinx FPGA Dev Board
. .
|_
Synchronous-DRAM Controller
. .
|_
scsi_chip
. .
|_
RS232 system controller
. .
|_
Programmable Interrupt Controller
. .
|_
Power Supply Sequencer
. .
|_
pci_mini
. .
|_
PCIe_mini_axi4s_wb
. .
|_
PCIe_mini (PCI-Express to Wishbone Bridge for Xilinx FPGAs)
. .
|_
PCIe_DS_DMA
. .
|_
PCIe SG DMA controller
. .
|_
PCI Target
. .
|_
PCI slave to WB master
. .
|_
PCI Express x1 16bit VERA testbench
. .
|_
PCI bridge
. .
|_
OCIDEC (OpenCores IDE Controller)
. .
|_
Memory Controller IP Core
. .
|_
External parallel port to internal wishbone master interface
. .
|_
AHBmaster for FPGA of microsemi
. .
|_
AC 97 Controller IP Core
.
|_
System on Module
. .
|_
SoM-ARM9-CycloneIVGX
. .
|_
OpenArty
.
|_
System on Chip
. .
|_
Zorro bus to Wishbone bridge
. .
|_
Z80 System on Chip
. .
|_
XuLA2-LX25 SoC
. .
|_
WishboneTK toolkit
. .
|_
Wishbone to AHB Bridge
. .
|_
Wishbone System6800/01
. .
|_
wishbone out port from b3 spec
. .
|_
WISHBONE DMA/Bridge IP Core
. .
|_
WISHBONE Conmax IP Core
. .
|_
WISHBONE Conbus IP Core
. .
|_
WISHBONE Builder
. .
|_
WB/OPB & OPB/WB Interface Wrapper
. .
|_
Taar Microprocessor
. .
|_
System09
. .
|_
system05
. .
|_
System-on-Chip Wire (SoCWire)
. .
|_
System-On-Chip based on bare Rocket-chip (RISC-V ISA)
. .
|_
STORM SoC
. .
|_
Soft MultiProcessor on FPGA
. .
|_
Simple AXI4-Lite bridges for IPbus and Wishbone
. .
|_
SimpCon - a Simple SoC Interconnect
. .
|_
SBA - Simple Bus Architecture
. .
|_
SardMIPS
. .
|_
rtf68kSys
. .
|_
rfid tag and reader
. .
|_
Real-time image processing
. .
|_
PSS (Programmable Supervisor for Systems-on-Chip)
. .
|_
Project Oberon with SDRAM
. .
|_
PLBv46 to Wishbone Bridge
. .
|_
PIF2WB
. .
|_
PDP-1 reimplementation
. .
|_
ORPSoC
. .
|_
Or1k SoC on Altera Embedded Dev Kit
. .
|_
or1200_soc
. .
|_
OpenSPARC-based SoC
. .
|_
OpenFIRE
. .
|_
OpenCL Board Support Package (BSP) for the Nallatech / Bittware 385A including dual 40 Gigabit Ethernet interfaces.
. .
|_
OMS8051 MINI
. .
|_
OC - H.264 Encoder SoC
. .
|_
NoCmodel
. .
|_
NoCem -- Network on Chip emulator
. .
|_
NoC(Network-on-Chip) Simulator
. .
|_
NoC based MPSoC
. .
|_
Next186MP3
. .
|_
Next186 SoC PC
. .
|_
MP3 decoder
. .
|_
minsoc
. .
|_
MaSoCist Soc builder/simulator
. .
|_
M16C5x
. .
|_
layer[2]
. .
|_
Keras to FPGA
. .
|_
Internal communication bus for FPGA
. .
|_
I2C Controller Wishbone Wrapper
. .
|_
H2 Forth SoC
. .
|_
Generic AXI to APB bridge
. .
|_
Generic AXI to AHB bridge
. .
|_
Generic AXI interconnect fabric
. .
|_
Generic AXI DMA
. .
|_
Generic APB register file
. .
|_
Generic AHB matrix
. .
|_
GECKO4 SoC co-design environment
. .
|_
GECKO3 SoC co-design environment
. .
|_
Experimental Unstable CPU
. .
|_
EPC RFID Transponder
. .
|_
Embedded FPGA Core
. .
|_
Embedded 32-bit RISC uProcessor with SDRAM Controller
. .
|_
ECO32
. .
|_
CPU Lecture
. .
|_
CMOD S6 SoC
. .
|_
CCSDS RX_TX_SoC
. .
|_
AXI4 Transactor and Bus Functional Model
. .
|_
AXI DMA 32 / 64 bits
. .
|_
Async-SDM-NoC
. .
|_
Assembler with VHDL User-defined Commands (AVUC)
. .
|_
Arm core
. .
|_
aoOCS - Wishbone Amiga OCS SoC
. .
|_
AHB to Wishbone Bridge
. .
|_
ahb system generator
. .
|_
AHB DMA 32 / 64 bits
.
|_
Processor
. .
|_
ZPU - the worlds smallest 32 bit CPU with GCC toolchain
. .
|_
Zip Cpu
. .
|_
Zet - The x86 (IA-32) open implementation
. .
|_
ZAP
. .
|_
z80control
. .
|_
Z3 - The Zork CPU
. .
|_
Yellow Star
. .
|_
YACC-Yet Another CPU CPU
. .
|_
Y80e - Z80/Z180 compatible processor extended by eZ80 instructions
. .
|_
Wishbone High Performance Z80
. .
|_
Wishbone BFM
. .
|_
VTACH - Bell Labs CARDIAC reimagined in Verilog
. .
|_
VLIW Processor
. .
|_
vhdl core of IC6821
. .
|_
V6502
. .
|_
v586
. .
|_
UoS Educational Processor
. .
|_
UCore
. .
|_
TV80
. .
|_
turbo 8051
. .
|_
TotalCPU
. .
|_
tinyVLIW8
. .
|_
TinyCPU
. .
|_
tiny8
. .
|_
Tiny64
. .
|_
Tiny Instruction Set Computer
. .
|_
Thor Superscaler
. .
|_
Theia: ray graphic processing unit
. .
|_
The Neptune Core
. .
|_
TG68K.C
. .
|_
TG68 - execute 68000 Code
. .
|_
T80 cpu
. .
|_
T6507LP
. .
|_
T65 CPU
. .
|_
T51 mcu
. .
|_
T48 µController
. .
|_
T400 µController
. .
|_
System68
. .
|_
system11
. .
|_
SXP (Simple eXtensible Pipeline ) Processor
. .
|_
Storm Core (ARM7 compatible)
. .
|_
Small Stack Based Computer Compiler
. .
|_
Software Aided Wishbone Extension for Xilinx (R) PicoBlaze (TM)
. .
|_
Small x86 subset core
. .
|_
Scarts Processor
. .
|_
SAYEH educational processor
. .
|_
S80186
. .
|_
S1 Core
. .
|_
RV01 RISC-V core
. .
|_
rtf8088
. .
|_
RTF65002
. .
|_
RISE Microprocessor
. .
|_
RISC_Core_I
. .
|_
RISCOmpatible
. .
|_
RISC5x
. .
|_
risc16f84
. .
|_
RISC Microcontroller
. .
|_
Register Oriented Instruction Sets
. .
|_
Reduced AVR Core for CPLD
. .
|_
Raptor64
. .
|_
r2000 Soc
. .
|_
QUARK RISK
. .
|_
qrisc32 wishbone compatible risc core
. .
|_
PPX16 mcu
. .
|_
Potato Processor
. .
|_
plasma with FPU
. .
|_
Plasma - most MIPS I(TM) opcodes
. .
|_
Pepelatz MISC
. .
|_
PDP-8 Processor Core and System
. .
|_
PDP-11/70 CPU core and SoC
. .
|_
pAVR
. .
|_
P16C5x
. .
|_
OpenRISC 2000
. .
|_
OpenRisc 1200 HP, Hyper Pipelined OR1200 Core
. .
|_
OpenRISC 1000 (old)
. .
|_
OpenRISC 1000
. .
|_
openMSP430
. .
|_
OpenFire Processor Core
. .
|_
OpenCPU32
. .
|_
opencpu
. .
|_
OpenCores54x DSP
. .
|_
Open8 uRISC
. .
|_
OoOPs - Out-of-Order MIPS (TM) Processor
. .
|_
oks8
. .
|_
ODESS Multicore Project
. .
|_
NextZ80
. .
|_
Next 80186 processor
. .
|_
NEO430 Processor (MSP430-compatible)
. .
|_
nCore
. .
|_
Navré AVR clone (8-bit RISC)
. .
|_
Natalius 8 bit RISC
. .
|_
NanoBlaze: the expandable processor
. .
|_
myBlaze
. .
|_
MSP430 CPU core in VHDL
. .
|_
MPX 32-bit CPU
. .
|_
MMU for Z80 and eZ80
. .
|_
MIPS_enhanced
. .
|_
mipsr2000
. .
|_
mips789
. .
|_
MIPS32 Release 1 with support for FPU and other COPs
. .
|_
MIPS32 Release 1
. .
|_
Mips-FaultTolerant
. .
|_
mips compatible barrel processor
. .
|_
miniMIPS Superscalar
. .
|_
miniMIPS
. .
|_
Minimal PDP8/L implementation with 4K disk monitor system
. .
|_
Mini-Risc core
. .
|_
MicroSimplez
. .
|_
MicroRISC II
. .
|_
microprocessor za208
. .
|_
MCPU - A minimal CPU for a CPLD
. .
|_
MCIP open
. .
|_
McAdam's RISC Computer Architecture
. .
|_
MC6803/6801 CPU
. .
|_
MB-Lite
. .
|_
M65C02
. .
|_
M32632 32-bit Processor
. .
|_
M1 Core
. .
|_
LXP32, a lightweight 32-bit CPU core
. .
|_
LocationPU
. .
|_
Lightweight 8080 compatible core
. .
|_
Lightweight 8051 compatible CPU
. .
|_
Leros: A Tiny Microcontroller for FPGAs
. .
|_
Leros-32
. .
|_
LEM1_9
. .
|_
Lattice 6502
. .
|_
KLC32
. .
|_
K68
. .
|_
JOP: a Java Optimized Processor
. .
|_
Ion - MIPS(tm) compatible CPU
. .
|_
i8080 compatible processor using Am29XX bit slice family and microcoded design
. .
|_
i650
. .
|_
HyperMTA
. .
|_
HPC-16
. .
|_
HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core
. .
|_
HiCoVec - a configurable SIMD CPU
. .
|_
HF-RISC
. .
|_
HD63701 compatible core
. .
|_
HC11 Compatible - Gator uProcessor
. .
|_
GPU
. .
|_
FPz8
. .
|_
FORTH processor with Java compiler
. .
|_
Fluid Core (A Reconfigurable Pipelined RISC processor)
. .
|_
Featherweight RISC-V
. .
|_
erm16
. .
|_
ELM Embedded Processor
. .
|_
Educational RISC Processor
. .
|_
Educational 16-bit MIPS Processor
. .
|_
Edge Processor (MIPS)
. .
|_
ecpu_alu
. .
|_
Distributed limited cores
. .
|_
Diogenes: Student RISC System
. .
|_
Data Flow Processor
. .
|_
cpu65c02_tc - R65C02 Processor Soft Core with accurate timing
. .
|_
cpu6502_tc - R6502 Processor Soft Core with accurate timing
. .
|_
Cpu Generator
. .
|_
Cowgirl
. .
|_
copyBlaze
. .
|_
Confluence OpenRisc 1000
. .
|_
Codezero OpenRISC Port
. .
|_
Classic 5-Stage Pipeline MIPS
. .
|_
ClaiRISC - runs 12bit opcode PIC family.
. .
|_
CF State Space Processor
. .
|_
Brainfuck CPU
. .
|_
BiRiscV - 32-bit dual issue RISC-V CPU
. .
|_
AX8 mcu
. .
|_
AVRtinyX61core
. .
|_
AVR HP, Hyper Pipelined AVR Core
. .
|_
AVR Core
. .
|_
Attiny Atmega Xmega core
. .
|_
Atlas Processor Core
. .
|_
ASPIDA sync/async DLX Core
. .
|_
ARM4U
. .
|_
Aquarius
. .
|_
Apollo Guidance Computer NOR eMulator
. .
|_
aoR3000
. .
|_
ao68000 - Wishbone 68000 core
. .
|_
ao486
. .
|_
An inventory of soft processor cores
. .
|_
Amber ARM-compatible core
. .
|_
Alwcpu - A light weight CPU
. .
|_
alt_ISA
. .
|_
AltOr32 - Alternative Lightweight OpenRisc CPU
. .
|_
ag_6502 soft core with phase-level accuracy
. .
|_
aeMB
. .
|_
ae18
. .
|_
A-Z80 CPU
. .
|_
8080 Compatible CPU
. .
|_
8051 core
. .
|_
8-bit uP
. .
|_
8-bit Piepelined Processor
. .
|_
8-bit microcontroller with extended peripheral set
. .
|_
68hc08
. .
|_
68hc05
. .
|_
6809 and 6309 Compatible core
. .
|_
6502VHDL
. .
|_
4004 CPU and MCS-4 family chips
. .
|_
32 bit Processor
. .
|_
1664 microprocessor
. .
|_
16-bit Open uRISC core Processor
. .
|_
16-bit CPU based loosely on Caxton Foster's Blue architecture
. .
|_
16 Bit Microcontroller
.
|_
Library
. .
|_
Versatile library
. .
|_
TTL Library
. .
|_
Srdy-Drdy Library
. .
|_
Robot Control Library
. .
|_
Real-time Clock
. .
|_
ratpack
. .
|_
Random Number Generator Library
. .
|_
Qaztronic's libraries
. .
|_
openVeriFLA - FPGA logic analyzer
. .
|_
MyGPU
. .
|_
Library of functions using/for DP streaming interface
. .
|_
Library of commonly used components
. .
|_
Library of common functions
. .
|_
Library of basic components with/for DP streaming interface
. .
|_
HDL-deflate
. .
|_
gh vhdl library
. .
|_
Funbase IP library
. .
|_
fixed_extensions
. .
|_
extension_pack
. .
|_
Common Design Environment
.
|_
ECC core
. .
|_
Yet Another Hamming Encoder and Decoder
. .
|_
Viterbi Decoder (AXI4-Stream compliant)
. .
|_
Ultimate CRC
. .
|_
Turbo Decoder
. .
|_
Spread Spectrum modulator and demodulator using BPSK
. .
|_
RS_5_3_GF256
. .
|_
Reed-Solomon Decoder/Encoder
. .
|_
Reed-Solomon Decoder (31, 19, 6)
. .
|_
Reed-Solomon Codec Generator
. .
|_
Reed Solomon Encoder/Decoder
. .
|_
Reed Solomon Encoder
. .
|_
Reed Solomon Decoder (204,188)
. .
|_
Reed Solomon (9,5) Encoder/Decoder
. .
|_
Product Code Iterative Decoder
. .
|_
PCI Express 16 bit CRC verilog file
. .
|_
ham_7_4_enc
. .
|_
Double error correcting (DEC) BCH encoder / decoder
. .
|_
Constellation Encoder
. .
|_
Configurable Hamming Generator
. .
|_
Configurable BCH Encoder and Decoder
. .
|_
CF LDPC Decoder
. .
|_
802.3an LDPC Encoder
. .
|_
802.3an LDPC Decoder
.
|_
DSP core
. .
|_
Wideband FFT
. .
|_
VIIRF - Versatile IIR Filter
. .
|_
Radix-2 SDF FFT
. .
|_
Quadrature Oscillator
. .
|_
Polyphase Decimation Filter
. .
|_
Pipelined fixed point elementary functions (div, sin, cos, exp, atan2, sqrt)
. .
|_
Pipelined FFT/IFFT 64 points processor
. .
|_
Pipelined FFT/IFFT 256 points processor
. .
|_
Pipelined FFT/IFFT 128 points processor
. .
|_
Pipelined DCT/IDCT
. .
|_
PID controller
. .
|_
NCO / Periodic Waveform Generator
. .
|_
Low-Pass IIR Filter
. .
|_
low-pass filter FIR
. .
|_
Low Power FIR Filter
. .
|_
IQ Phase and Gain Correction
. .
|_
IMA ADPCM Encdoer & Decoder
. .
|_
IIR
. .
|_
Hilbert Transformer
. .
|_
Generic FIR Filter
. .
|_
Generic FIR filter
. .
|_
G-FIR TF/DF
. .
|_
Floating-point FFT/IFFT
. .
|_
FirGen/MultGen
. .
|_
filtro_FIR
. .
|_
FFT-based FIR Filter
. .
|_
Fast Hadamhard Transforms
. .
|_
Dynamic resizable streaming the base 2 FFT
. .
|_
DSP WishBone Compatible Cores
. .
|_
Double Clocked FFT Core
. .
|_
DDS Synthesizer
. .
|_
Correlation statistics core
. .
|_
Configurable High Speed Viterbi Decoder
. .
|_
CIC-filter core
. .
|_
CIC filter
. .
|_
CIC Decimation Filter
. .
|_
CF FIR Filter
. .
|_
Cascaded FIR Filter
. .
|_
Canny Edge Detector
. .
|_
Biquad IIR Filter Core
. .
|_
all-pole IIR filters
. .
|_
Adaptive LMS equalizer
. .
|_
A Linked List Run-Length-Based Single-Pass Connected Component Analysis
.
|_
Crypto core
. .
|_
XTEA Crypto Core
. .
|_
XTEA Core
. .
|_
Twofish Core
. .
|_
twofish 128/192/256
. .
|_
Tiny Encryption Algorithm
. .
|_
The Grain stream cipher
. .
|_
SystemC/Verilog MD5
. .
|_
SystemC/Verilog DES
. .
|_
Simple to use SHA-2 algorithm
. .
|_
Simple Camellia Crypto Core
. .
|_
Simon Core
. .
|_
SHA3 (KECCAK)
. .
|_
SHA256 HASH CORE
. .
|_
SHA1 Secure Hash Algorithm
. .
|_
SHA-256 Core
. .
|_
SHA cores
. .
|_
Secure Hash Standard 256 bits
. .
|_
Salsa20StreamCipher
. .
|_
RTEA 128/256
. .
|_
RSA Processor
. .
|_
RSA
. .
|_
rc6 cryptography
. .
|_
RC4 Pseudo-random stream generator
. .
|_
Present Cipher Encryption Core
. .
|_
Present - a lightweight block cipher
. .
|_
Pipelined AES
. .
|_
Nugroho Free Hash Cores
. .
|_
Nugroho Free Crypto Cores
. .
|_
NOEKEON Core (lightweight block cipher)
. .
|_
Montgomery modular multiplier and exponentiator
. .
|_
Mini AES
. .
|_
MD5 Pipelined
. .
|_
IOTA PoW Pearl-Diver Curl-P81
. .
|_
IDEA core
. .
|_
HIGHT Crypto Core
. .
|_
high throughput and low area aes core
. .
|_
High Radix Montgomery RSA Crypto Core
. .
|_
Hardware implementation of SHA-3 (keccak) algorithm
. .
|_
gost28147-89
. .
|_
GOST 28147-89
. .
|_
Galois Counter Mode Advanced Encryption Standard GCM-AES
. .
|_
Flexible Design of a Modular Simultaneous Exponentiation Core
. .
|_
fast AES-128 Encryption only cores
. .
|_
DESX Core
. .
|_
DESLX Core
. .
|_
DESL Core
. .
|_
DES/Triple DES IP Cores
. .
|_
DES Core
. .
|_
csa
. .
|_
Crypto-PAn
. .
|_
Compact CLEFIA for FPGA
. .
|_
Chip-to-chip authentication with PUF and RSA
. .
|_
Camellia cores
. .
|_
BTCMiner - Open Source Bitcoin Miner
. .
|_
Bluespec MD6
. .
|_
Bluespec Cryptosorter
. .
|_
Bitcoin Double SHA256
. .
|_
Basic RSA Encryption Engine
. .
|_
Basic DES Crypto Core
. .
|_
B-163 EC Arithmetic
. .
|_
Avalon AES ECB-Core (128, 192, 256 Bit)
. .
|_
AES128
. .
|_
AES-VHDL
. .
|_
AES-128 Encryption
. .
|_
AES SystemVerilog behavioral model
. .
|_
AES encryption all keylength
. .
|_
AES decryption IP (128 bit)
. .
|_
AES Decryption Core for FPGA
. .
|_
AES cores (compact)
. .
|_
AES core modules
. .
|_
AES-1
. .
|_
AES
. .
|_
3DES (Triple DES) / DES (VHDL)
. .
|_
128/192 AES
. .
|_
AES (Rijndael) IP Core
.
|_
Coprocessor
. .
|_
xgate
. .
|_
ORSoC Graphics Accelerator
. .
|_
JT51 - YM2151 compatible core
. .
|_
Floating Point Unit
. .
|_
CPU Code Execution Timestamp
. .
|_
CF Reconfigurable Computing Array
.
|_
Communication controller
. .
|_
YANU - UART with predictive interrupt events on Rx/Tx buffers state
. .
|_
xSPi
. .
|_
WishboneAXI
. .
|_
wishbone uart controller 8 bit
. .
|_
Wishbone SD Card Controller
. .
|_
Wishbone Register Bank Intercon Multi-master Multi-slave
. .
|_
Wishbone protocol to axi4 protocol
. .
|_
Wishbone LPC Host and Peripheral Bridge
. .
|_
Wiegand Controller (SIA AC-01-1996.10)
. .
|_
wb_uart
. .
|_
vSPI
. .
|_
Versatile IO
. .
|_
USB to UART
. .
|_
USB Host Core
. .
|_
USB FT232H Avalon-MM interface
. .
|_
USB Device Core
. .
|_
USB 2.0 Function Core
. .
|_
USB 1.1 PHY
. .
|_
USB 1.1 Host and Function IP core
. .
|_
USB 1.1 Function IP Core
. .
|_
USB 1.1 Simulation (VHDL)
. .
|_
USB 1.1 PHY (VHDL)
. .
|_
ULPI Wrapper
. .
|_
UDP/IPv4 for 10G Ethernet
. .
|_
UDP/IP Core
. .
|_
UART8SYSTEMC
. .
|_
uart6551
. .
|_
UART16750
. .
|_
UART with PLB interface
. .
|_
UART To SPI
. .
|_
UART to Bus
. .
|_
UART to / from fiber optic
. .
|_
Uart block
. .
|_
UART 16550 core
. .
|_
Uart (FIFO cpu interface) with SV Self-Checking Testbench
. .
|_
tiny SPI
. .
|_
TIME SLOT INTERCHANGE DIGITAL SWITCH
. .
|_
TI TLV320AIC1106 PCM Codec Altera Avalon IP core
. .
|_
TDM controller
. .
|_
TCP/IP socket
. .
|_
TCP IP Core
. .
|_
SystemVerilog uart16550
. .
|_
SystemC USB1.1 IP Core
. .
|_
Super-I/O (SIO) controller
. .
|_
Stepper Motor Controller
. .
|_
SSP_UART
. .
|_
SSP_Slv
. .
|_
SPORT Interface
. .
|_
SPIxIF
. .
|_
spislave
. .
|_
spigpio
. .
|_
SPI-slave Wishbone-Master
. .
|_
SPI Verilog Master & Slave modules
. .
|_
SPI serial DAC interface
. .
|_
SPI Master/Slave Interface
. .
|_
spi master receiver for ADC (AD747x)
. .
|_
SPI Master Lightweight
. .
|_
SPI Flash controller
. .
|_
SPI core
. .
|_
SPI Controller for AD/DA chips on S3E/A/AN Starter Kits
. .
|_
SPI controller core
. .
|_
SPI based SD card controller
. .
|_
SPDIF Transmitter
. .
|_
SPDIF Interface
. .
|_
SpaceWireSystemC
. .
|_
SpaceWire Light
. .
|_
SpaceWire
. .
|_
smbus_if
. .
|_
Smartcard interface (ISO7816-3)
. .
|_
Small 1-wire (onewire) master, with Altera tools integration
. .
|_
Single Slot PCM Interface
. .
|_
Simple UART for FPGA
. .
|_
Simple RS232 UART
. .
|_
Simple Asynchronous Serial Controller
. .
|_
Simple AES3 / SPDIF receiver
. .
|_
SGMII
. .
|_
Serializer / Deserializer for audio fiber optic
. .
|_
Serial Uart
. .
|_
Serial UART
. .
|_
Serial to parallel converter
. .
|_
Serial ATA Host Bus Adapter Core for Virtex 6
. .
|_
SDRAM AXI4
. .
|_
SDHC Self Configuring Core
. .
|_
SD/MMC Controller
. .
|_
SD/MMC Bootloader
. .
|_
SD/eMMC/MMC card emulator
. .
|_
sd card controller
. .
|_
Scan Based Serial Communication
. .
|_
Saturn
. .
|_
SATA PHY
. .
|_
SATA Controller
. .
|_
SATA 2 HOST Controller
. .
|_
RXAUI Interface and XAUI to RXAUI Interface Adapter
. .
|_
rtfSimpleUart
. .
|_
RS232
. .
|_
RS232
. .
|_
RapidIO IP library
. .
|_
Quadrature Decoder / Counter
. .
|_
Quad SPI Flash Controller
. .
|_
PS2 Core
. .
|_
PS/2 Host Controller
. .
|_
PLB-to-WB Bridge
. .
|_
Playstation 2 network adaptor IC CXD9731
. .
|_
Pipelined wishbone to AXI converter
. .
|_
PC-FPGA Communication Platform
. .
|_
opb_usblite
. .
|_
OPB-compatible OneWire Master
. .
|_
OPB SPI Slave
. .
|_
OP2P (OpenPeerToPeer Interface)
. .
|_
One Wire Master
. .
|_
OHCI Full/Low-Speed USB Host Controller
. .
|_
OFDM modem
. .
|_
neopixel ws2812
. .
|_
nec ir remote control decoder
. .
|_
Multimicrophone Interface
. .
|_
Minimal UART Core
. .
|_
Minimac - the minimalist Ethernet MAC
. .
|_
Manchester UART
. .
|_
Manchester to UART converter
. .
|_
Manchester Decoder for Wireless
. .
|_
MADI Receiver
. .
|_
lzs
. .
|_
LPC ROM emulator on USB dongle FPGA core set
. .
|_
JTAG Slave / BoundaryScan Slave
. .
|_
JTAG Master
. .
|_
Iso7816_3_Master
. .
|_
IrDA
. .
|_
IPv4 Ethernet Packet Creator and Transmitter
. .
|_
IEEE 802.15.4 CRC
. .
|_
IEEE 802.15.4 Core (physical layer)
. .
|_
i8255 realisation in Verilog
. .
|_
I2S to WishBone
. .
|_
I2S to Parallel Interface
. .
|_
I2S to Paralell ADC/DAC controller
. .
|_
I2S Interface
. .
|_
i2c_to_wb
. .
|_
i2cgpio
. .
|_
I2C Traffic Logger
. .
|_
I2C Slave
. .
|_
I2C Repeater
. .
|_
I2C Multiple Bus Controller
. .
|_
I2C master/slave Core
. .
|_
I2C Master Slave Core
. .
|_
I2C controller core
. .
|_
HyperTransport Tunnel
. .
|_
HDLC controller
. .
|_
HDB3/B3ZS Encoder+Decoder
. .
|_
Hardware Assisted IEEE 1588 IP Core
. .
|_
GPIB (IEEE-488) controller
. .
|_
General-Purpose I/O (GPIO) Core
. .
|_
Gamepads
. .
|_
FTDI Async FIFO I/F to Wishbone Bridge
. .
|_
FT245R interface
. .
|_
FT2232H USB Avalon Core
. .
|_
FPGA remote slow control via UART 16550
. .
|_
FPGA Communication Framework
. .
|_
FireWire (IEEE 1394)
. .
|_
Fade - Light L3 Ethernet protocol for transmission of data from FPGA to embedded PC
. .
|_
EZUSB communication core
. .
|_
Ethernet Switch on Configurable Logic
. .
|_
Ethernet SMII
. .
|_
Ethernet MAC 10/100 Mbps
. .
|_
Ethernet 10GE MAC
. .
|_
Ethernet 10GE Low Latency MAC
. .
|_
Ethernet 100/1000 Mbps
. .
|_
Etherblade.net - FPGA ethernet line-rate encapsulator (EoIP, EoMPLS, PBB etc)
. .
|_
EPP v1.9
. .
|_
EBU/spdif to I2S project
. .
|_
E1-G.703,G.704,G.706 framer/deframer
. .
|_
E1 Framer/Deframer
. .
|_
DQPSK Mapper
. .
|_
Documented Verilog UART
. .
|_
DMX512 transceiver
. .
|_
DMT Transceiver
. .
|_
Core1990: Interlaken protocol
. .
|_
Cheap Ethernet interface
. .
|_
CAN Protocol Controller
. .
|_
Bluetooth baseband controller
. .
|_
Bluespec 802.11a Transmitter
. .
|_
Bitwise addressable GPIO
. .
|_
baud generator
. .
|_
Automatic BAUD rate generator
. .
|_
Asynchronous SPI master
. .
|_
Async 8b/10b enc/dec
. .
|_
ARINC 429 Transmitter and Receiver
. .
|_
APB to SPI
. .
|_
APB to I2C
. .
|_
Another Wishbone Controlled UART
. .
|_
Another SPI Controller (with FIFO)
. .
|_
AMI / HDB1 Line Codes
. .
|_
ahci
. .
|_
adat receiver
. .
|_
A VHDL CAN Protocol Controller
. .
|_
a VHDL 16550 UART core
. .
|_
8b10b Encoder/Decoder
. .
|_
1G Ethernet DPI
. .
|_
1G Ethernet ARP
. .
|_
1G eth UDP / IP Stack
. .
|_
16 Quadrature Amplitude Modulator and Demodulator
. .
|_
10_100_1000 Mbps tri-mode ethernet MAC
. .
|_
10G Ethernet MAC
. .
|_
1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)
. .
|_
100 MB/s Ethernet MAC Layer Switch
. .
|_
10/100M Ethernet-FIFO convertor
.
|_
Prototype board
. .
|_
ZTEX USB-FPGA Module 2.14
. .
|_
ZTEX USB-FPGA Module 2.13
. .
|_
ZTEX USB-FPGA Module 2.04
. .
|_
XENIE programmable 10GBASE-T FPGA module
. .
|_
USB-FPGA Module 2.16
. .
|_
USB-FPGA Module 1.15
. .
|_
USB FPGA MODULE 1.2
. .
|_
USB FPGA Module 1.11
. .
|_
Technologic Systems TS-7300 FPGA Computer
. .
|_
Spartan 6 PCIexpress card
. .
|_
Spartan 6 + PIC32 + USB + Ethernet
. .
|_
Raggedstone PCI Spartan-3 board
. .
|_
Plataforma de Hardware Reconfigurable
. .
|_
PCI card with Xilinx X3CS500E
. .
|_
PCI Board
. .
|_
OpenRisc Development Board
. .
|_
OPENCORES Application Board 1 (OAB1)
. .
|_
Open Design Prototype Board
. .
|_
OMRP Prototype board v2
. .
|_
OCRP-2 board
. .
|_
OCRP-1 board
. .
|_
Milkymist One interactive VJ station
. .
|_
Micro FPGA Board
. .
|_
MAXII-Evalboard
. .
|_
LPC ROM, SPI ROM, 8bit ROM emulator on Artec Dongle II board
. .
|_
Linux & Xilinx FPGA Dev Board
. .
|_
kiss-board
. .
|_
Internal Logic State Analyzer
. .
|_
IIE-PCI Board
. .
|_
IGOR - A microprogrammed LISP machine
. .
|_
Griva Basic board
. .
|_
Game-Trees FPGA implementation (Othello Game)
. .
|_
EUS FS - Alice II - Embeddable Single Board Computer
. .
|_
EtraxFS & Xilinx FPGA dev board with building blocks
. .
|_
EP2C35 Board
. .
|_
de1_olpcl2294_system
. .
|_
Butterfly Light
. .
|_
Audio DSP PCI Card
. .
|_
arduFPGA iCE40UP5K
. .
|_
aes220 High-Speed USB FPGA mini-module
. .
|_
ACEX 1K50 board
.
|_
Arithmetic core
. .
|_
[128bit] Pseudo Random Number Generator Using Linear-feedback Shift Registers
. .
|_
YAC - Yet Another CORDIC Core
. .
|_
Xilinx Virtex FLoating Point
. .
|_
VIterbi_Tx_Rx
. .
|_
Viterbi HDL Code Generator
. .
|_
Versatile counter
. .
|_
Unsigned serial divider
. .
|_
Universal multi-function CORDIC
. .
|_
True matrix 3x3 multiplier
. .
|_
trigonometric functions (degrees) in double fpu
. .
|_
Tiny Tate Bilinear Pairing
. .
|_
Ternary (3-input) Adder
. .
|_
Tate Bilinear Pairing
. .
|_
Tanh Approximation Custom Instruction for NIOS II
. .
|_
suslik scalar risc cpu
. .
|_
Superscalar Version Of DLX
. .
|_
Single Clock Unsigned Division Algorithm
. .
|_
Single 14 Segment Display Driver with Limited ASCII Decoder
. .
|_
SineAndCosineTable
. .
|_
Signed integer divider
. .
|_
Signed / unsigned multiplier and divider with prime number generator as test circuit
. .
|_
Requantizer
. .
|_
Reed-Solomon Decoder
. .
|_
Reconfigurable Hardware Platform
. .
|_
Ray Tracing Arithmetic Engine
. .
|_
radix 4 complex fft
. .
|_
QuadFixedPoint32 Arithmetic Unit
. .
|_
PYRAMID Integer Multiplier unit
. .
|_
Priority Encoder
. .
|_
Population Counter Generator
. .
|_
pipeline mips in vhdl
. .
|_
PID Controler
. .
|_
Parametrized FFT engine
. .
|_
Parameterizable integer square root by the digit-by-digit method
. .
|_
Parameterizable adder tree
. .
|_
openFPU64
. .
|_
Numbert sort device O(N)
. .
|_
Non Linear Pseudo Random Generator
. .
|_
Multiply-Accumulate Operation (MAC)
. .
|_
Multiplier library
. .
|_
Model of hybrid classical-quantum computing method
. .
|_
MODBUS Implementation in VHDL
. .
|_
mod3_calc
. .
|_
MESI Coherency InterSection Controller
. .
|_
Maximum/Minimum binary tree finder
. .
|_
LZRW1 Compressor Core
. .
|_
Logarithm function, base-2, single-cycle
. .
|_
LFSR-Random number generator
. .
|_
LCD162B Behavior Model
. .
|_
Huffman Decoder
. .
|_
HIERARCHICAL Integer Multiplier unit
. .
|_
Heap sorter for FPGA
. .
|_
HCSA adder and Generic ALU based on HCSA
. .
|_
Hardware Load Balancer for Multi-Stage Software Router
. .
|_
Hardware implementation of Binary Fully Digital Phase Locked Loop
. .
|_
Hardware Division Units
. .
|_
GNExtrapolator
. .
|_
Generic LFSR Generator
. .
|_
Generic Galois LFSR
. .
|_
Generic Booth Multiplier
. .
|_
Gaussian Noise Generator
. .
|_
FT816Float - Floating point accelerator
. .
|_
FPU Double VHDL
. .
|_
FPU
. .
|_
FPGA-based Median Filter
. .
|_
Floating-Point Logarithm Unit
. .
|_
Floating Point Adder and Multiplier
. .
|_
Fixed-point quadratic polynomial
. .
|_
Fixed Point Square Root (Recursive Algorithm)
. .
|_
Fixed Point Math Library for Verilog
. .
|_
Fixed Point Arithmetic Modules
. .
|_
Elliptic Curve Group
. .
|_
DVB-S2 LDPC Decoder
. .
|_
double_fpu_verilog
. .
|_
Discrete Cosine Transform core
. .
|_
DCT - Discrete Cosine Transformer
. .
|_
cr_div - Cached Reciprocal Divider
. .
|_
CRCAHB
. .
|_
CORDIC core
. .
|_
CORDIC arctangent for IQ signals
. .
|_
Configurable Parallel Scrambler
. .
|_
configurable CRC core
. .
|_
configurable cordic core in verilog
. .
|_
Complex Operations ISE for NIOS II
. .
|_
Complex Multiplier
. .
|_
Complex Gaussian Pseudo-random Number Generator
. .
|_
Complex Arithmetic Operations
. .
|_
CF Floating Point Multiplier
. .
|_
CF FFT
. .
|_
CF Cordic
. .
|_
Cellular Automata PRNG
. .
|_
cavlc decoder
. .
|_
Booth Array Multiplier
. .
|_
Bluespec SystemVerilog Reed Solomon Decoder
. .
|_
Binary to BCD conversions, with LED display driver
. .
|_
BCD adder
. .
|_
Anti-Logarithm (square-root), base-2, single-cycle
. .
|_
ANN
. .
|_
AES128
. .
|_
Adder library
. .
|_
8 bit Vedic Multiplier
. .
|_
5x4Gbps CRC generator designed with standard cells
. .
|_
4-bit system
. .
|_
2D FHT
. .
|_
1 bit adpcm codec
.
|_
Memory core
. .
|_
ZBT SRAM Controller
. .
|_
Wishbone Interface for SPI FLASH
. .
|_
Wishbone FLASH Interface for Parallel FLASH
. .
|_
Wishbone DDR3 SDRAM Controller
. .
|_
wb_size_bridge
. .
|_
wb_async_mem_bridge
. .
|_
Versatile memory controller
. .
|_
Versatile FIFO
. .
|_
USB NAND Flash Reader
. .
|_
synchronous_reset_fifo with testbench
. .
|_
Stack design
. .
|_
SSRAM interface
. .
|_
srl_fifo
. .
|_
sp_ram to 3p_ram WISHBONE Wrapper
. .
|_
Single Port ASRAM
. .
|_
Scratch DDR SDRAM Controller
. .
|_
RAM_wb
. .
|_
RAM library
. .
|_
Parametrized FIFO based on SRL16E
. .
|_
openHMC
. .
|_
Open FreeList
. .
|_
OPB PSRAM Controller
. .
|_
NAND Controller (ONFI compliant)
. .
|_
Memory sizer
. .
|_
Memory cores
. .
|_
High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline
. .
|_
High Performance Dynamic Memory Controller
. .
|_
High Latency Bursting WISHBONE Wrapper for Xilinx MIG
. .
|_
Generic FIFOs
. .
|_
Generic FIFO
. .
|_
Functional simulation models for commercially available RAMs
. .
|_
FIFO library
. .
|_
FAT32 Parser
. .
|_
DPSFmnCE
. .
|_
DirectMappedCacheController
. .
|_
DDR3 Synthesizable BFM
. .
|_
DDR2 SDRAM Controller
. .
|_
DDR2 mem controller for Digilent Genesys Board
. .
|_
DDR2
. .
|_
DR SDRAM Controller Core
. .
|_
CFI flash controller
. .
|_
CF Interleaver
. .
|_
BRSFmnCE
. .
|_
Asynchronous WISHBONE-compatible SDRAM controller
. .
|_
2Q cache
. . .
|_
8/16/32 bit SDRAM Controller
. .
|_
16-bit SDRAM Controller
. .
|_
DDR3 SDRAM controller
Thư Viện Đề Tài Luận Văn - Đồ Án
Thư Viện Hệ Thống Nhúng - Embeded System Books
Thư Viện Kỹ Thuật Số - Digital Technical Books
.
|_
Máy Biến Trạng Thái - State Machine Design Books
.
|_
Kỹ Thuật Số Cơ Bản - Basic Digital Technical Books
Thư Viện VIP Model - Verification IP (VIP) Directory
Thư viện về FPGA-CPLD - FPGA & CPLD Specifications
Tài liệu DFT -Design For Test and Tools User Guide
Tài liệu về CMOS - CMOS Structure Documents
Tài Liệu Ngôn Ngữ Script Linux (cshell, bash shell, perl script language)
Thư Viện Bài Tập Semicon
Tài Liệu Xây Dựng Môi Trường - Verification Simulation Books
Tài Liệu System Verilog - System verilog Books
Thư Viện Về Phần Mềm trong Thiết Kế Vi Mạch - Tools Usage Guide in IC design
Tài Liệu STA - Static Timing Analysis Books
Tổng Hợp Tần Sồ - Logic Synthesis & Tool Guide Books
Tài Liệu Verilog, VHDL HDL - Verilog & VHDL Books
.
|_
Tài Liệu VHDL - VHDL Language Books
.
|_
Verilog HDL Books
Tài Liệu Thiết Kế SOC - SOC (System on Chip) Design Books
Tài Liệu Thiết Kế ASIC - ASIC design Books
Tài Liệu Thiết Kế Vi Mạch - IC Design Reference Books
Bài Học Vi Mạch Hay - Good Lectures from Educational Courses
Thư Viện Thiết Kế Mẫu Tham Khảo - Example Design for Study
CPU Core + IPs core + Full chip Specifications
.
|_
Bus Specifications
. .
|_
OpenCore Bus Architecture Specification
. .
|_
Bus Bridge (arbiter) Specification
. .
|_
Synopsys Bus Architecture Specification
. .
|_
IBM Bus Architecture Specification
. .
|_
Intel Bus Architecture Specification
. .
|_
Hitachi Bus Architecture Specification
. .
|_
ARM Bus Architecture Specifications
.
|_
SOC Specifications
.
|_
IP Core Specifications
. .
|_
I2S Specifications
. .
|_
Interrupt Controller Specifications
. .
|_
SRAM Controller Specifications
. .
|_
SDHC Controller Specifications
. .
|_
TDM Specifications
. .
|_
RTC (Real Time Clock) Specifications
. .
|_
DMA Controller Specifications
. .
|_
IrDA Specifications
. .
|_
SPI Specifications
. .
|_
I2C Specifications
. .
|_
UART Specifications
. .
|_
SATA Controller Specifications
. .
|_
Watchdog Timer (WDT) Specifications
. .
|_
Security Specifications
. .
|_
Cache Controller Specifications
. .
|_
Serial Flash Controller Specifications
. .
|_
NOR Flash Controller Specifications
. .
|_
NAND FLASH Controller Specifications
. .
|_
SRAM Controller Specifications
. .
|_
On Chip Memory Specifications
. .
|_
SRAM Controller Specifications
. .
|_
DDR Controller Specifications
. .
|_
Bluetooth Specifications
. .
|_
USB 1.0 Specifications
. .
|_
PCIE Specifications
. .
|_
SCI Specifications
. .
|_
PWM Specifications
. .
|_
Ethernet Specifications
. .
|_
USB PHY Specifications
. .
|_
PCI Specifications
. .
|_
USB 2.0 Specification
.
|_
CPU Core Specifications
. .
|_
Open Core Specifications
. .
|_
Hitachi Core Specifications
. .
|_
Intel Core Specifications
. .
|_
IBM Core Specifications
. .
|_
ARM Core Specifications
Tài Liệu Mở Từ Semicon
Ordering
:
Newest first
Oldest first
Most popular
Alphabetical
Category
Reverse
Search by
:
Any words
All words
Exact phrase
Regular Expression
Not
Search where
:
Name
Description
Giải nhất thiết kế vi mạch TP HCM - Đề tài về chip RISC-V
Khai giảng Khóa Học Thiết Kế Vi Mạch 04-2025
Từ sinh viên xuất sắc của MIT, người phụ nữ làm rung chuyển ngành công nghệ chip: Đưa công ty khỏi bờ vực phá sản, trở thành huyền thoại chấn động ngành công nghệ
Việt Nam và cuộc đua bán dẫn: Cổ điển hay lượng tử?
TRAO CHỨNG CHỈ TỐT NGHIỆP LỚP THỰC TẬP THÁNG 6,7 NĂM 2024
Vì sao nhiều "ông lớn" công nghệ giúp Việt Nam đào tạo nhân lực?
Chủ tịch tập đoàn Meta sẽ sang Việt Nam phát biểu tham luận tại Hội thảo về AI và bán dẫn vào ngày 1/10
Việt Nam cần 500.000 nhân lực IT, lương lên đến 3.000 USD/tháng
HỌC TIẾNG ANH TẠI SEMICON
Hé lộ về công ty ít người biết nhưng không hề kém cạnh Nvidia: Vốn hoá tăng hơn 200% trong 2 năm, hàng loạt ông lớn công nghệ phải phụ thuộc, âm thầm 'càn quét' ngành hot nhất nhì thế giới
TPHCM lập quỹ 5 triệu USD đào tạo 40 nghìn kỹ sư thiết kế vi mạch
Mặt trận mới không ngờ trong cuộc chiến chip
Tham gia khóa thực tập sinh thiết kế vi mạch tại Semicon
Khai Giảng Lớp Đào Tạo ứng dụng UVM cho Verification
Khóa Học Cao Cấp Thiết Kế Vi Mạch Số
Lớp Khai Giảng Khóa Đào Tạo Ngôn Ngữ System Verilog cho Verification
TSMC công bố tiến trình 1.6nm, iPhone 18 sẽ là thiết bị đầu tiên được hưởng lợi?
