Staff/Principal Design Engineer (Physical Design)

Overview

• Located in San Diego, CA
• DA Digital SD department
• Download Application

Primary Job Responsibilities:

Responsible for all aspects of physical design and implementation. Participating in the efforts of establishing physical design methodologies, flow automation, chip and block floorplan, power/clock distribution, chip assembly, P&R, and timing closure.

Education/Experience Requirement:

• BS/MS in EE or equivalent required with 5-7 years of experience in physical design of submicron SoC products (e.g. microprocessor based SoCs and large transport chips).
• Strong hands-on  physical verification (Caliber).  Work with LEF/GDS issue with IP, library and PDK.
• Strong hands-on floorplanning, clock tree synthesis, timing closure, signal integrity, IR drop analysis, ECO implementation, and physical design verification.
• Experience in 40 nm technologies, low-power design, custom placement and implementation of high-speed (>1 GHz) clocks.
• Knowledge of all aspects of chip development process with proficiency in backend design tools and methodologies.
• Coding in scripting languages such as Perl, Tcl, and UNIX shell, etc.
• Experience in interfacing with design and STA teams.
• Experience in Cadence physical design tools is a plus.
• Self-driven individual and a good team player.