Senior Physical Design Engineer – Static Timing Analysis
AppliedMicro - Vietnam
We are currently seeking Senior Physical Design engineers for several full time, direct hire opportunities in the Ho Chi Minh City, Vietnam area. The key to this job is STA or Static Timing Analysis.
In this role, you will be responsible for the timing closure / timing constraints development on our cutting edge ARMv8 based server on chip solutions (X-Gene) and our communication products (X-Weave) that will be the backbone of future data centers.
You will be interacting on a daily basis with our design team worldwide and will work on the latest technology nodes available in the industry.
Responsibilities:
Define timing constraints at block and top level across all modes (Functional / BIST / SCAN / JTAG/Timing Driven Placement & Route/Clock Distribution).
Enhance and develop our TCL based timing sign off environment.
Provide Implementation and timing feedback to both front end and layout teams.
Perform timing closure across all corners to ensure successful ECO tapeout following our aggressive deadlines.
Compétences et expérience souhaitées
Qualifications:
* Experience with Verilog or HDL languages and tools.
* Experience with SoC design flow.
* Experience in STA with writing constraints, timing analysis & executing timing ECOs.
* Experience in scripting languages (PERL, TCL, shell, etc.)
* Experience in ASIC methodologies and tools
(RTL Compiler, Synopsys Primetime, Cadence Tempus, LEC, CDC …)
* Good communication and teamwork skills.
* Good English communications skills, both verbal and writing.
* BS/MS/Ph.D. in Electrical Engineering/Computer Engineering or equivalent and 2-7 years of digital ASIC design/verification experience.
