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Design For Test At All Levels (manager/ Senior/ Junior)

Uniquify Viet Nam One Member LLC Level 7, Thien Son building, 5 Nguyen Gia Thieu street, ward 6, district 3, HCMC Level 5, Indochina Riverside Tower building, 74 Bach Dang street, Hai Chau 1 ward, Hai Chau district, Da Nang city

Work Location: Da Nang, Ho Chi Minh

What We Can Offer

13th month salary
Performance bonus
Personal accident and Health insurances package for you and your family

You Should Be Best At

STA Constraints Development Experience

Knowledge Of Verilog And/or Vhdl

DFT Experience, Including Atpg, Jtag, Mbist and Trade-offs Between Test Quality and Test Time

What You Will Do

We are seeking a sharp and highly motivated person whom our experienced ASIC design team can teach and train into an excellent ASIC design engineer. Candidate will work closely with our industry experienced DFT, physical design and/or logical design ASIC team developing multi-million gate state of the art System-on-Chip (SoC) designs. Candidate will gain understanding and practical knowledge in DFT of ASICs. This is a great opportunity for anyone who wants to start a career in the ASIC design industry.

What You Are Good At

1. DFT Manager:
• The ideal candidate will have 5+ years of DFT experience, leading DFT efforts for SOC designs
• Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Experience developing DFT specifications and driving DFT architecture and methods for designs a plus
• Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools
• Knowledge of industry standards DFT and design tools
• Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues a plus
• Experience with STA constraints development and analysis for DFT modes and SDF simulations a plus.

2. Senior DFT Engineer:
• The ideal candidate will have 2+ years of DFT experience, leading DFT efforts for SOC designs
• Knowledge about industrial standards and any/all of the following practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools
• Knowledge of industry standards DFT and design tools
• Possible Experience with STA constraints development and analysis for DFT modes and SDF simulations a plus.

3. Junior DFT Engineer:
• Completion of undergraduate program in Electrical Engineering or Computer Engineering.
• Strong analytical and critical thinking skills.
• Good communication skills, positive attitude, and ability to work in a team environment.
• Exposure to a scripting languages such as TCL, Perl, and/or Make is a plus.
• Good understanding of Fundamentals of Synchronous logic design.
• Coursework in digital IC design a plus.
• Experience with Verilog coding and DFT implementation a plus.
• Project or industry experience in ASIC is a plus.

About Our Company

Uniquify Viet Nam One Member LLC Level 7, Thien Son building, 5 Nguyen Gia Thieu street, ward 6, district 3, HCMC Level 5, Indochina Riverside Tower building, 74 Bach Dang street, Hai Chau 1 ward, Hai Chau district, Da Nang city

Contact person: HR Department
Company size: 25-99

Headquartered in Silicon Valley, Uniquify(www.uniquify.com) is a privately held ASIC design services and semiconductor IP solutions provider. The company has design centers in Santa Clara, California, Pune, India, Ho Chi Minh city and Da Nang city; and it maintains sales offices in Austin, Santa Clara, Seoul, Taipei and Tel Aviv. Uniquify provides leading edge SoC design and IP solutions. We offer a wide range of “ideas2silicon” services that span design specification, RTL, logic design/verification, physical implementation, and manufacturing operations. Perseus, our proprietary design management system allows us to deliver consistent design closure and reduced schedules on even the most complex SoC designs

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