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Các câu phỏng vấn và trả lời về Verilog (Phần 2)

Question 11. Tell Me Structure Of Verilog Code You Follow?

Answer :

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation

`timescale 1 ns / 10 ps

module name (input and outputs);

// parameter declarations

parameter parameter_name = parameter value;

// Input output declarations

input in1;

input in2; // single bit inputs

output [msb:lsb] out; // a bus output

// internal signal register type declaration - register types (only assigned within always statements). reg register

variable 1;

reg [msb:lsb] register variable 2;

// internal signal. net type declaration - (only assigned outside always statements) wire net variable 1;

// hierarchy - instantiating another module

reference name instance name (

.pin1 (net1),

.pin2 (net2),

.pinn (netn)

);

// synchronous procedures

always @ (posedge clock)

begin

end

// combinatinal procedures

always @ (signal1 or signal2 or signal3)

begin

end

assign net variable = combinational logic;

endmodule

Question 12. Difference Between Verilog And Vhdl?

Answer :

Compilation

VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data types

VHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.

Question 13. Can You Tell Me Some Of System Tasks And Their Purpose?

Answer :

$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.

The most useful of these is $display.This can be used for displaying strings, expression or values of variables.

Here are some examples of usage.

$display("Hello oni");

--- output: Hello oni

$display($time) // current simulation time.

--- output: 460

counter = 4'b10;

$display(" The count is %b", counter);

--- output: The count is 0010

$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where the user can enter commands; $finish exits the simulator back to the operating system

Question 14. Can You List Out Some Of Enhancements In Verilog 2001?

Answer :

In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity list . In Verilog 2001, we can use comma as shown in the example below.

// Verilog 2k example for usage of comma

always @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches,  Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below

module memory (

input r,

input wr,

input [7:0] data_in,

input [3:0] addr,

output [7:0] data_out

);

Question 15. Write A Verilog Code For Synchronous And Asynchronous Reset?

Answer :

Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk

Eg: always @ (posedge clk )

begin if (reset)

. . . end

Asynchronous means clock independent so reset must be present in sensitivity list.

Eg: Always @(posedge clock or posedge reset)

begin

if (reset)

. . . end

Question 16. What Is Pli?why Is It Used?

Answer :

Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with programs written in C language. It also provides mechanism to access internal databases of the simulator from the C program.

PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel and hardware related features of Verilog and sequential flow of C - using PLI.

Question 17. There Is A Triangle And On It There Are 3 Ants One On Each Corner And Are Free To Move Along Sides Of Triangle What Is Probability That They Will Collide?

Answer :

Ants can move only along edges of triangle in either of direction, let’s say one is represented by 1 and another by 0, since there are 3 sides eight combinations are possible, when all ants are going in same direction they won’t collide that is 111 or 000 so probability of not collision is 2/8=1/4 or collision probability is 6/8=3/4

Question 18. How To Write Fsm Is Verilog?

Answer :

There r mainly 4 ways 2 write fsm code

- Using 1 process where all input decoder, present state, and output decoder r combine in one process.

- Using 2 process where all comb ckt and sequential ckt separated in different process

- Using 2 process where input decoder and persent state r combine and output decoder seperated in other process

- Using 3 process where all three, input decoder, present state and output decoder r separated in 3 process.

Question 19. What Is Difference Between Freeze Deposit And Force?

Answer :

$deposit(variable, value);

This system task sets a Verilog register or net to the specified value. variable is the register or net to be changed; value is the new value for the register or net. The value remains until there is a subsequent driver transaction or another $deposit task for the same register or net. This system task operates identically to the ModelSim force -deposit command.

The force command has -freeze, -drive, and -deposit options. When none of these is specified, then -freeze is assumed for unresolved signals and -drive is assumed for resolved signals. This is designed to provide compatibility with force files. But if you prefer -freeze as the default for both resolved and unresolved signals.

Question 20. Will Case Infer Priority Register If Yes How Give An Example?

Answer :

Yes case can infer priority register depending on coding style

reg r;

// Priority encoded mux,

always @ (a or b or c or select2)

begin

r = c;

case (select2)

2'b00: r = a;

2'b01: r = b;

endcase

end

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