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## Các câu phỏng vấn và trả lời về Verilog (Phần 3)

Question 21. Given The Following Verilog Code, What Value Of "a" Is Displayed?

always @(clk) begin

a = 0;

a <= 1;

\$display(a);

end

This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

- Active Events (blocking statements)

- Inactive Events (#0 delays, etc)

- Monitor Events (\$display, \$monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue".

The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.

Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.

Question 22. What Is The Difference Between The Following Two Lines Of Verilog Code?

#5 a = b;

a = #5 b;

#5 a = b;

Wait five time units before doing the action for "a = b;".

a = #5 b; The value of b is calculated and stored in an internal temp register,After five time units, assign this stored value to a.

Question 23. What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog Code?

'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage :`timescale / reference_time_unit : Specifies the unit of measurement for times and delays. time_precision: specifies the precision to which the delays are rounded off.

Question 24. What Is The Difference Between === And == ?

output of "==" can be 1, 0 or X.

output of "===" can only be 0 or 1.

When you are comparing 2 nos using "==" and if one/both the numbers have one or more bits as "x" then the output would be "X" . But if use "===" outpout would be 0 or 1.

e.g:  A = 3'b1x0

B = 3'b10x

A == B will give X as output.

A === B will give 0 as output.

"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the input is X output will be X

"===" is used for comparison of X also.

Question 25. How To Generate Sine Wav Using Verilog Coding Style?

The easiest and efficient way to generate sine wave is using CORDIC Algorithm.

Question 26. What Is The Difference Between Wire And Reg?

(wire,tri)Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element. Assigned values only within an always statement or an initial statement. The main difference between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a->b, if there is no connection in a and b, wire loose value. But reg can hold the value even if there in no connection. Default values:wire is Z,reg is x.

Question 27. How Do You Implement The Bi-directional Ports In Verilog Hdl?

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

input oe;

input clk;

input [7:0] inp;

output [7:0] outp;

inout [7:0] bidir;

reg [7:0] a;

reg [7:0] b;

assign bidir = oe ? a : 8'bZ ;

assign outp = b;

// Always Construct

always @ (posedge clk)

begin

b <= bidir;

a <= inp;

end

endmodule

Question 28. What Is Verilog Case (1) ?

wire [3:0] x;

always @(...) begin

case (1'b1)

x[0]: SOMETHING1;

x[1]: SOMETHING2;

x[2]: SOMETHING3;

x[3]: SOMETHING4;

endcase

end

The case statement walks down the list of cases and executes the first one that matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the statement that will get executed (or selected by the logic).

Question 29. Why Is It That "if (2'b01 & 2'b10)..." Doesn't Run The True Case?

This is a popular coding error. You used the bit wise AND operator (&) where you meant to use the logical AND operator (&&).

Question 30. What Are Different Types Of Verilog Simulators ?

There are mainly two types of simulators available.

- Event Driven

- Cycle Based

Event-based Simulator:

This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is calculated for every device it propagates through during a clock cycle. Full Event-based simulators support 4-28 states; simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; full timing calculations for all devices; and the full HDL standard. Event-based simulators are like a Swiss Army knife with many different features but none are particularly fast.

Cycle Based Simulator:

This is a Digital Logic Simulation method that eliminates unnecessary calculations to achieve huge performance gains in verifying Boolean logic:

- Results are only examined at the end of every clock cycle; and

- The digital logic is the only part of the design simulated (no timing calculations). By limiting the calculations, Cycle based Simulators can provide huge increases in performance over conventional Event-based simulators.

Cycle based simulators are more like a high speed electric carving knife in comparison because they focus on a subset of the biggest problem: logic verification.

Cycle based simulators are almost invariably used along with Static Timing verifier to compensate for the lost timing information coverage

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