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Job code: EHW14-01

– Responsible for module or IP design including specification, RTL design and random verification

– Bachelor or Master Degree in Information Technology/Computer Engineering/Computer Science/Telecoms/Electronics
– At least 3 years’ experience in Electronics Engineering/Computer Engineering with Module/IP logic design and verification field
– Have basic knowledge of USB3.0 xHCI, USB2.0 EHCI, PCIe3.0. eMMC, Ethernet
– Good at C coding (experience in Assembly language is a plus)
– Solid understanding of RTL Design (Verilog is preferable), System Verilog
– Experience with random verification for IP using System Verilog, VMM, UVM
– Have knowledge of using random verification model (ex; Synopsys or Cadence).
– Have knowledge of Perl, TCL, UNIX shell, or equivalent scripting languages.
– Good written and oral communication & interpersonal skills
– Have good team working skill and good relationship with the others
– Long-term working commitment

Expected starting date: March 1, 2014

We offer a competitive compensation and benefits package. Interested candidates can send applications from now until January 10, 2014 by following ways:

• Apply online below

• E-mail CV to Địa chỉ email này đã được bảo vệ từ spam bots, bạn cần kích hoạt Javascript để xem nó. ; or

• Post CV to:

  Ms. Ho Thi Ngoc Ha

  Human Resource Dept.,

  Renesas Design Vietnam Co., Ltd., Tan Thuan Road,

  Tan Thuan EPZ., Dist. 7, HCMC

* Only short list candidates will be contacted.

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