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Review SystemC Modules

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1. Introduction
Modules are the basic building block within SystemC to partition a design. Modules allow designers to break complex systems into smaller more manageable pieces. 


2. Content

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Modules help split complex designs among a number of different designers in a design group. Modules allow designers to hide internal data representation and algorithms from other modules. This forces designers to use public interfaces to other modules, and the entire system becomes easier to change and easier to maintain. Modules are similar to module in Verilog and Entity in VHDL.

A Module should in basic should contain ports, constructor, and methods/functions to work on the ports. Below is list of parts of a module.

  • ports
  • Internal Variables
  • Constructor
  • Internal Methods.


In SystemC modules are declared with SystemC keyword SC_MODULE. Below is syntax of a SC_MODULE.

Syntax :

1 SC_MODULE("module_name") {

 2   // module body

 3 }


  • SC_MODULE : Macro or reserve word
  • module_name : Any valid module name

If you don't want to use SC_MODULE macro and want to write in pure C++ syntax, then you can write as below.

 1 class module_name : sc_module {

 2   // Module body

 3 }

This form of declaration resembles a typical C++ declaration of a struct or a class. The macro SC_MODULE provides an easy and very readable way to describe the module.


 1 // All systemc code should include systemc.h file

 2 #include "systemc.h"

 3 // SC_MODULE is macro, hello_world is module name

 4 SC_MODULE (hello_world) {

 5   // Body of module hello_world

 6 };


Module Ports
Module Ports pass data to and from the processes of a module to the external world as in Verilog and VHDL. You declare a port direction as inout, or inout. You also declare the data type of the port as any C++ data type,



SystemC data type, or user defined type.
Types of Ports


  • in : Input Ports
  • out : Output Ports
  • inout : Bi-direction Ports
    Port modes sc_in, sc_out, and sc_inout are predefined by the SystemC class library.
    Syntax :

Here :

  • port_direction : One of the sc_in,sc_out,sc_inout
  • type : Data type
  • variable : Valid variable name

Example Module Ports

  1 #include "systemc.h"


  3 SC_MODULE (first_counter) {

  4   sc_in_clk     clock ;      // Clock input of the design

  5   sc_in<bool>   reset ;      // active high, synchronous Reset input

  6   sc_in<bool>   enable;      // Active high enable signal for counter

  7   sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter


  9   // Rest of body


 10 }
Module Signals



Ports are used for communicating outside the module. For communicating within a SystemC module we use signals. Signals are like wires in Verilog. Signals can be of any legal data types.
Signal are also used for connecting two modules ports in parent module. Lets say we have two child modules A and B, this two modules are used in parent module C, then wires are used for connecting ports of module A and B with each other.
Syntax :
 sc_signal type variable;


Here :

  • sc_signal : Reserved word
  • type : Data type
  • variable : Valid variable name

Example Module Signal

 1 #include "systemc.h"


 3 SC_MODULE (counter) {

 4   sc_signal <bool>        reset ;     

 5   sc_signal <bool>        enable;     

 6   sc_signal <sc_uint<4> > counter_out;


 8   // Rest of body

 9 }

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