SCI [Serial Communications Interface] is an asynchronous serial communications bus used between uP [CPUs] and peripheral devices [EPROMs for example].
Two signal lines are used with SCI: TXD [Transmit], and RXD [Receive].
The two wire SCI bus operates in Full-duplex mode [transmitting and receiving at the same time.
SCI uses either an 8 or 9 bit data format, with data being sent using NRZ [non-return-to-zero] encoding.
The SCI bus may also be setup as a single wire interface, using the TXD pin to both send and receive data.
Normally data is sent as 8 or 9 bit words [least significant bit first]. A START bit marks the beginning of the frame. The start bit is active low. The figure above shows a framed 8 bit data word. The data word follows the start bit. A parity bit may follow the data word [after the MSB] depending on the protocol used. A mark parity bit [always set high] may be used, a space parity bit [always set low] may be used, or an even/odd parity bit may be used. The even parity bit will be a 1 if the number of ones/zeros is even, or a zero if there are an odd number. The odd parity bit will be high if there is an odd number of ones/zeros in the data field. No parity bit is used in the example above. A stop bit will normally follow the data field [or parity bit if used]. The stop bit is used to bring [or insure] the signal rests at a logic high following the end of the frame; so when the next start bit arrives it will bring the bus from a high to low. Idle characters are sent as all ones with no start or stop bits. The RT clock rate is 16 times the incoming baud rate. The RT clock is re-synchronized after every start bit.
I believe there are 13-bit baud rate selections ranging between 110 to 38400 baud. There are three modes of operation: Run mode, Wait mode [low power state], and Stop mode [low power state]. However these modes may apply to the operation of the IC I was reading about.
I assume the electrical interface is derived from the device being used. A 5 volt part will drive the bus at normal 5v TTL/CMOS levels. and a 3.3 volt part drives the bus at normal LVTTL/LVCMOS level. The interface between devices being left up to the designer to insure one chip will talk to the next chip in the design. Note; this is not the same SCI bus as the Scalable Coherent Interface bus; IEEE Std 1596.
I assume the electrical interface is derived from the device being used. A 5 volt part will drive the bus at normal 5v TTL/CMOS levels. and a 3.3 volt part drives the bus at normal LVTTL/LVCMOS level. The interface between devices being left up to the designer to insure one chip will talk to the next chip in the design. Note; this is not the same SCI bus as the Scalable Coherent Interface bus; IEEE Std 1596.
