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Serial ATA (SATA) Interface Bus

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SATA Message Frame 

   Serial ATA Description

     The Serial ATA bus [SATA] is the serial version of the IDE [ATA] spec. SATA uses a 4 conductor cable with two differential pairs [Tx/Rx], plus an additional three grounds pins and a separate power connector. Data runs at 150MBps [1.5GHz] using 8B/10B encoding and 250mV signal swings, with a maximum bus length of 1 meter.

Later SATA enhancements move the data transfer speed to; 300MBps [3.0Gbps], and then 600MBps [6.0Gbps]. The current speed for SATA is 300Mbps [3Gbps]. Shielded external SATA [eSATA] data cable runs out to a maximum of between 3 feet and 6 feet. eSATA cables are used external to the chassis or case. Just released xSATA which is an external interface out to 8 meters.

SATA Protocol

The SATA Frame structure used between Host and Device is shown in the graphic below. The frame is made up of multi Dwords, which are in turn encapsulated by flow control and CRC information. The SATA frame begins with a Start-of-frame [SOF]. The SOF is followed by the Frame Information Structure [FIS]. Then the Cyclic Redundancy Code [CRC] is placed in the frame. The final block in the message is an End-of-Frame [EOF]. SATA uses a 32bit CRC [calculated over the contents of a (FIS) Frame Information Structure], stored as the 'Dword'.

The 32-bit CRC polynomial is X32+ X26+ X23+ X22+ X16+ X12+ X11+ X10+ X8+ X7+ X5+ X4+ X2+ X + 1.


SATA Message Frame
Serial ATA [SATA] Bus Protocol Frame

SATA Electrical

Serial ATA uses LVDS [EIA/TIA-644] with voltages of 250mV; while the obsolete parallel ATA interface is based on TTL signaling levels and rates. Serial ATA is a point-to-point interface where each device is directly connected to the host via a dedicated link. Because Serial ATA uses a dedicated link, adding another drive to the computer will have no impact on bandwidth. With Serial ATA the additional hard drive uses a separate SATA link, while the older IDE parallel standard [PATA] would see a degradation in speed because the drives would share the same link band width. The Bit Encoding used is: Non Return to Zero (NRZ) encoding for data communication on a differential two wire bus. The use of NRZ encoding ensures compact messages with a minimum number of transitions and high resilience to external disturbance. The termination resistor is 100 Ohms [+/- 5 Ohms] differential.

SATA Physical

Serial ATA uses only 4 signal pins, improving pin efficiency over the parallel ATA interface which uses 26 signal pins going between devices [over an 80 conductor ribbon cable onto a 40 pin header connector].
Serial ATA also provides the opportunity for devices to be 'hot-plugged', devices may be inserted or removed while the system is powered on. The pinout tables for Serial ATA are listed below.

The primary function of Serial ATA bus is to form an interface between the Motherboard and the Hard Disk Drive [HDD]. The Hard Drive may have a SATA connector and a legacy PATA data connector, with a legacy PATA power connector, so the device may function in either a legacy [older] motherboard or a currently produced motherboard. In this case the mother board S-ATA interface would be developed from a peripheral add-on board and not the motherboard. Power connectors on a HDD are header pins for a P-ATA interface and card-edge finger blades in the case of S-ATA. Some drive connectors shield the S-ATA power connector preventing their use, so you must use the P-ATA power pins to supply power to the drive. Terms used to describe the obsolete Harddrive interface which preceded the SATA interface include; IDE, Parallel ATA, PATA, and P-ATA.

 

Serial ATA Jitter Description

Deterministic Jitter [DJ], and Total Jitter [TJ] are listed in the table below. TJ is the addition of DJ and Random Jitter [RJ].
The Driver Output Jitter listed is the maximum allowed jitter from the driver. The Receiver Input jitter is the maximum jitter the receiver will tolerate.

SATA Jitter
Description Driver
Output
Driver PCB
Connector
Receiver PCB
Connector
Receiver
Input
DJ TJ DJ TJ DJ TJ DJ TJ
A0,p-p(UI) 0.15 0.33 0.175 0.355 0.25 0.43 0.275 0.455
n0 5 5 5 5 5 5 5 5
A1,p-p(UI) 0.2 0.45 0.22 0.47 0.35 0.6 0.37 0.62
n1 250 250 250 250 250 250 250 250
A2,p-p(UI) 40 40 40 40
n2 25000 25000 25000 25000

The table does not account for UI error due to frequency skew. The final two rows list Total Jitter [TJ] only.

SATA Interface IC's

Serial ATA uses LVDS [EIA/TIA-644] with voltages of 250mV.

Atmel {Serial ATA Bridge IC, PATA to SATA Converter}

Genesys logic {Serial ATA Gen II 3.0Gbps PHY IP Core}

JMicron Technology Corporation {1 to 5-ports Serial ATA II Port Multiplier with RAID function support, PCI Express to SATA II Host Controller}

LSI Corporation {8-Port 3Gbps SATA Controller}

Marvell {Serial ATA Bridge IC, PATA to SATA Converter}

Mixel {Quad Gigabit Transceiver IP}

PLX Technology {FireWire/USB to SATA Controllers, USB to SATA Controllers, Consumer Network Attached Storage (NAS) SoC, Consumer Direct Attached Storage (DAS) SoC}

Silicon Storage Technology, Inc. 'SST' {SATA Disk Controller IC}

Soft Mixed Signal Corporation 'SMS' {SATA PHY transceiver IP}

 

Parallel ATA, IDE Description

PATA information is provided below for reference, how ever with the addition of SATA ~ PATA is now obsolete, you can refer to the Parallel ATA bus page for more information. Serial ATA uses 250mV switching levels instead of 5 volt TTL levels [reducing power requirements], a smaller cable [increasing air flow in the chassis], operates at 150MBps instead of 133MBps, and is Hot-Swappable.
Here is a chart of Hard Drive Transfer Speeds. The chart compares each version of PATA [ATA-1, ... ATA-7, and the 2 versions of SATA.

Serial ATA is not compatible with the IDE [Parallel ATA] because the connectors are different, the voltage levels are different, and SATA sends a bit at a time while PATA sends 16 bits at once. The two bus types will not interface with one another; PATA will not mate with SATA. The IDE bus will not connect to the SATA bus. Converter boards are available which translate Serial ATA to Parallel ATA interfaces for a cost around 50 dollars.

ATA-1 (IDE), [Obsolete] 8.3MBytes/sec, 8 or 16 bit data width, 40 pin data ribbon cable/connector. With a maximum of 2 devices on the bus. Using PIO Modes 0, 1 or 2. Performed no bus error correction.

ATA-2 (EIDE, or Fast ATA), [Obsolete] 16.6MBytes/sec, 8 or 16 bit data width, 40 pin data ribbon cable/connector. With a maximum of 4 devices on the bus. Using PIO Modes 0, 1, 2, 3, or 4

ATA-3, [Obsolete] 16MBytes/sec, 16 bit data width, 40 pin data ribbon cable/connector. Using PIO Modes 0, 1, 2, 3, or 4 and Multiword DMA modes 1 and 2. Runs with 120nS Strobes (rising edge to rising edge). Includes CRC.

ATA-4 Ultra-ATA/33, [Obsolete] 33MBytes/sec, 16 bit data width, 40 pin data ribbon cable/connector. Using PIO Modes 0, 1, 2, 3, or 4 and Multi-word DMA modes 1 and 2 and Ultra DMA modes 0, 1, and 2. Runs at a 60nS rate, using both edges of a 120nS Strobe.

ATA-5 Ultra-ATA/66, 66MBytes/sec, 16 bit data width 40-pin data connector/80 pin cable, with the additional 40 pins being Ground. Using PIO Modes 0, 1, 2, 3, or 4 and Multiword DMA modes 1 and 2 and Ultra DMA modes 0, 1, 2, 3 and 4. Runs at a 30nS rate, using both edges of a 60nS Strobe.

ATA-6 Ultra-ATA/100, 100MBytes/sec,16 bit data width 40 pin data connector/80 pin cable, with the additional 40 new pins being Ground. Using PIO Modes 0, 1, 2, 3, or 4 and Multiword DMA modes 1 and 2 and Ultra DMA modes 0, 1, 2, 3, 4 and 5.

ATA-7 Ultra-ATA/133, 133MBytes/sec,16 bit data width 40 pin data connector/80 pin cable, with the additional 40 new pins being Ground. 

Lần cập nhật cuối ( Thứ sáu, 31 Tháng 5 2013 16:03 )  
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