Verilog DUT

  1 // Simple Verilog Memory Model

  2 module memory(

  3 address,     // Address bus port

  4 data_in,     // Data input port

  5 data_out,    // Data output port

  6 read_write,  // Read/Write Enable

  7 chip_en      // Chip select

  8 );

  9

 10 input [7:0] address;

 11 input [31:0] data_in;

 12 output [31:0] data_out;

 13 input read_write, chip_en;

 14

 15 reg [31:0] mem [0:255];

 16

 17 always @ (address or data_in or read_write or chip_en)

 18 if (read_write == 1 && chip_en == 1) begin

 19   mem[address] = data_in;

 20 end

 21

 22 assign data_out = (read_write == 0 && chip_en == 1) ? mem[address] : 0;

 23

 24 endmodule

 25

 26 // Top level testbench code

 27 module tb();

 28

 29 // All the signals that need to be driven from

 30 // SystemC testbench needs be declared as reg

 31 reg [7:0] addr;

 32 reg [31:0] wdata;

 33 wire [31:0] rdata;

 34 reg         wr;

 35 reg         cs;

 36 reg         clk;

 37

 38 // Connect the Verilog Memory DUT

 39 memory dut (addr,wdata,rdata,wr,cs);

 40

 41 initial begin

 42   clk = 0;

 43   // Connect the systemC testbench here

 44   $memory_tb(clk,rdata,addr,wr,cs,wdata);

 45   $dumpfile("memory.vcd");

 46   $dumpvars();

 47 end

 48 // Clock generator

 49 always  #1  clk = ~clk;

 50

 51 endmodule

SystemC Mem Type

  1 #ifndef MEM_T_H

  2 #define MEM_T_H

  3 

  4 class mem_t {

  5   public:

  6     mem_t () {}

  7     virtual ~mem_t() {}

  8 

  9     sc_uint<8>      addr;

 10     sc_uint<32>     data;

 11 

 12     // Define an assign operator

 13     mem_t& operator=(const mem_t& rhs) {

 14       addr=rhs.addr; 

 15       data=rhs.data; 

 16       return *this;

 17     }

 18 

 19     // Define a comparison operator

 20     friend bool operator==(const mem_t& a, const mem_t& b) {

 21       if (a.addr  ! = b.addr) {return false;}

 22       if (a.data  ! = b.data) {return false;}

 23       return true;

 24     }

 25 

 26     // Define ostream method to print data

 27     friend ostream& operator<< (ostream& os, const mem_t& mem) {

 28       os << " Address : " << mem.addr << " Data : " << mem.data;

 29       return os;

 30     }

 31 };

 32 

 33 #endif

SystemC Mem Type Extension

  1 #ifndef MEM_T_EXT_H

  2 #define MEM_T_EXT_H

  3 

  4 SCV_EXTENSIONS(mem_t) {

  5   public:

  6     scv_extensions< sc_uint<8> > addr;

  7     scv_extensions< sc_uint<32> > data;

  8     SCV_EXTENSIONS_CTOR(mem_t) {

  9       SCV_FIELD(addr);

 10       SCV_FIELD(data);

 11     }

 12 };

 13 

 14 #endif

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