SystemC Ports

  1 #ifndef MEMORY_TB_PORTS_H

  2 #define MEMORY_TB_PORTS_H

  3

  4 struct tagInput {

  5   char  *clk;

  6   char  *rdata;

  7 };

  8

  9 struct tagOutput {

 10   unsigned long wr;

 11   unsigned long cs;

 12   unsigned long addr;

 13   unsigned long wdata;

 14   unsigned long done;

 15 };

 16

 17 typedef struct tagInput    INVECTOR;

 18 typedef struct tagOutput  OUTVECTOR;

 19

 20 #endif

SystemC Testbench

  1 #include "systemc.h"

  2 #include "memory_txGen.h"

  3 #include "memory_tb_ports.h"

  4 #include "memory_tb_exports.h"

  5 #include "strings.h"

  6 

  7 // Instantiate Testbench

  8 memory_txGen  u_memory_txGen("u_memory_txGen");

  9 // Declare Signals to connect tb

 10 sc_signal <bool>             clk;

 11 sc_signal <sc_uint<8> >      addr;

 12 sc_signal <bool>             wr;

 13 sc_signal <bool>             cs;

 14 sc_signal <sc_uint<32> >     wdata;

 15 sc_signal <sc_uint<32> >     rdata;

 16 sc_signal <bool>             done;

 17 // Top-Level testbench

 18 void init_sc() {

 19   // Port mapping

 20   u_memory_txGen.clk        (clk  );

 21   u_memory_txGen.addr       (addr );

 22   u_memory_txGen.wr         (wr   );

 23   u_memory_txGen.cs         (cs   );

 24   u_memory_txGen.wdata      (wdata);

 25   u_memory_txGen.rdata      (rdata);

 26   u_memory_txGen.done       (done );

 27   // VCD Tracing:

 28   //   Trace file creation

 29   sc_trace_file* tf;

 30   tf = sc_create_vcd_trace_file("memory_tb");

 31         ((vcd_trace_file*)tf)->sc_set_vcd_time_unit(-9);

 32   //   Signals to be traced

 33   sc_trace(tf, clk, "clk");

 34   sc_trace(tf, addr, "addr");

 35   sc_trace(tf, wr, "wr");

 36   sc_trace(tf, cs, "cs");

 37   sc_trace(tf, wdata, "wdata");

 38   sc_trace(tf, rdata, "rdata");

 39   // Initialize SC

 40   sc_start(0);

 41   cout<<"@"<<sc_time_stamp()<<" Started SystemC Schedular"<<endl;

 42 }

 43 // Convert Char to sc_unit

 44 // This is required if more then 64 bits are

 45 // required for port width

 46 sc_uint<32> str2scuint(char *data) {

 47   sc_uint<32>  udata;

 48   for (int i = 31; i >= 0; i--) {

 49     if (*(data+i) == 49) {

 50       udata[31-i] = 1;

 51     } else {

 52       udata[31-i] = 0;

 53     }

 54   }

 55   return(udata);

 56 }

 57 // String to bool conversion

 58 bool str2bool(char *data) {

 59   bool  udata;

 60   udata = (*data == 49) ? true:false;

 61   return(udata);

 62 }

 63 // Sample the HDL signals and driver systemC data types

 64 void sample_hdl(void *Invector) {

 65   INVECTOR *pInvector = (INVECTOR *)Invector;

 66   clk    = str2bool(pInvector->clk);

 67   rdata  = str2scuint(pInvector->rdata);

 68 }

 69 // Drive systemC signals to HDL

 70 void drive_hdl(void *Outvector) {

 71   OUTVECTOR *pOutvector = (OUTVECTOR *)Outvector;

 72   pOutvector->wr = wr.read();

 73   pOutvector->cs = cs.read();

 74   pOutvector->addr = addr.read();

 75   pOutvector->done =  done;

 76   pOutvector->wdata = wdata.read();

 77 }

 78 // Advance SystemC Simulation time

 79 void advance_sim(unsigned long simtime) {

 80   sc_start(simtime);

 81 }

 82 // Top level testbench controller

 83 void exec_sc(void *invector, void *outvector, 

 84  unsigned long simtime) {

 85   sample_hdl(invector);  // Input-Stimuli

 86   advance_sim(simtime);  // Advance Simulator

 87   drive_hdl(outvector);  // Output Vectors

 88 }

 89 // Terminate SystemC schedular

 90 void exit_sc() {

 91   cout<<"@"<<sc_time_stamp()<<" Stopping SystemC Schedular"<<endl;

 92   sc_stop();

 93 }

PLI Interface File

  1 #include   

  2 #include 

  3 

  4 #include "vcsuser.h"

  5 

  6 // SystemC methods 

  7 #include "memory_tb_ports.h"

  8 #include "memory_tb_exports.h"

  9 

 10 static int sc_init_done = 0;

 11 

 12 //calltf routine: turns on asynchronous callbacks to the misctf

 13 //routine whenever an argument to the system task changes value.

 14 int sc_memory_calltf() {

 15   if (sc_init_done == 0) {

 16     // Initialize SystemC Model

 17     init_sc(); 

 18     sc_init_done = 1;

 19   }

 20   // Turn-On Asynchronous Call-Back

 21   tf_asynchon();  

 22   return(0);

 23 }

 24 

 25 //misctf routine: Serves as an interface between Verilog simulation

 26 //and the testbench.  Called whenever the testbench inputs change value,

 27 //reads the input values, and passes the values to the SystemC, and

 28 //writes the SystemC outputs into simulation.

 29 int sc_memory_misctf(int user_data, int reason, int paramvc)

 30 {

 31   #define  SC_IN_CLK     1  /* system task arg 1 clk     input  */

 32   #define  SC_IN_RDATA   2  /* system task arg 2 rdata   input  */

 33   #define  SC_OUT_ADDR   3  /* system task arg 3 addr    output */

 34   #define  SC_OUT_WR     4  /* system task arg 4 wr      output */

 35   #define  SC_OUT_CS     5  /* system task arg 5 cs      output */

 36   #define  SC_OUT_WDATA  6  /* system task arg 6 wdata   output */

 37 

 38   static unsigned long SimNow = 0;

 39   // Testbench ports

 40   static INVECTOR   invector;

 41   static OUTVECTOR  outvector;

 42   // If HDL requested simulation termination

 43   if (reason == reason_finish) {

 44     exit_sc();

 45   }

 46   // abort if misctf was not called for a task argument value change

 47   if (reason  ! = REASON_PARAMVC) {

 48     return(0);

 49   }

 50   // abort if task argument that changed was a model output 

 51   if (paramvc  ! = SC_IN_RDATA && paramvc  ! = SC_IN_CLK)  { 

 52     return(0);

 53   }

 54   // Read current HDL values into systemC testbench 

 55   invector.rdata  = acc_fetch_value(acc_handle_tfarg(SC_IN_RDATA), "%b", 0);

 56   invector.clk    = acc_fetch_value(acc_handle_tfarg(SC_IN_CLK), "%b", 0);

 57   // Execute the systemC testbench with  delta time  

 58   exec_sc(&invector, &outvector, (tf_gettime()-SimNow));

 59   SimNow = tf_gettime();

 60   // Write the systemC Testbench outputs onto the Verilog signals

 61   tf_putp(SC_OUT_ADDR, outvector.addr);

 62   tf_putp(SC_OUT_WR, outvector.wr);

 63   tf_putp(SC_OUT_CS, outvector.cs);

 64   tf_putp(SC_OUT_WDATA, outvector.wdata);

 65   // If systemC requests termination, then ask Verilog simulator 

 66   // to terminate

 67   if (outvector.done) {

 68     tf_dofinish();

 69   }

 70   return(0);

 71 }

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