SystemC TxGen Header File

  1 #ifndef MEMORY_TXGEN_H

  2 #define MEMORY_TXGEN_H

  3 

  4 #include "systemc.h"

  5 #include "scv.h"

  6 #include "mem_t.h"

  7 #include "mem_t_ext.h"

  8 

  9 SC_MODULE (memory_txGen) {

 10   sc_in<bool>          clk;   // Clock input

 11   sc_out<sc_uint<8> >  addr;  // Address output

 12   sc_out<bool>         wr;    // Write enable

 13   sc_out<bool>         cs;    // Chip select

 14   sc_out<sc_uint<32> > wdata; // Write data

 15   sc_in<sc_uint<32> >  rdata; // Read data

 16   sc_out<bool>         done;  // Testing done

 17 

 18   void test(); // Method which implements test

 19 

 20   SC_CTOR(memory_txGen) {

 21     SC_CTHREAD(test,clk.pos());

 22   }

 23 };

 24 

 25 #endif

SystemC TxGen 

1 #include "memory_txGen.h"

  2 

  3 void memory_txGen::test() {

  4   scv_smart_ptr   object;

  5   int error = 0;

  6   // Drive low on all signals input to DUT

  7   addr  = 0;

  8   wr    = 0;

  9   cs    = 0;

 10   wdata = 0; 

 11   done  = 0;

 12   wait(1); // wait for one clock

 13   cout<<"@"<<sc_time_stamp()<<" Starting the memory write/read test"<<endl;

 14   for(int i = 0; i < 10;i++) {

 15     // Get the next random address and data object

 16     object->next();

 17     //------------------------------------------

 18     //  Do Memory Write

 19     //------------------------------------------

 20     // Drive the addess

 21     addr  = object->addr.read();

 22     // Drive the data

 23     wdata = object->data.read();

 24     // Drive Chip Select

 25     cs    = 1;

 26     // Drive write enable

 27     wr    = 1;

 28     cout<<"@"<<sc_time_stamp()<<" Writing address : "<< object->addr <<endl;

 29     wait(1); // Wait for one clock

 30     cs    = 0; // Deassert chip select

 31     wr    = 0; // Deassert write enable

 32     wait(1); // Wait for one clock

 33     //------------------------------------------

 34     //  Do Memory Read from Same Address

 35     //------------------------------------------

 36     cs    = 1; // Assert the chip select

 37     cout<<"@"<<sc_time_stamp()<<" Reading address : "<< object->addr <<endl;

 38     wait(1);

 39     // Compare the data written with read data

 40     if (rdata  ! = wdata) {

 41       error ++; // If error increment counter

 42       cout<<"@"<<sc_time_stamp()<<" Error : Write data : " << 

 43         wdata << " Read data : " << rdata << endl;

 44     } else {

 45       cout<<"@"<<sc_time_stamp()<<" Match : Write data : " << 

 46         wdata << " Read data : " << rdata << endl;

 47     }

 48     cs    = 0; // Deassert the chip selct

 49     wait(1);

 50   }

 51   // Request for simulation termination

 52   if (error > 0) {

 53     cout << "=======================================" << endl;

 54     cout << " SIMULATION FAILED" << endl;

 55     cout << "=======================================" << endl;

 56   } else {

 57     cout << "=======================================" << endl;

 58     cout << " SIMULATION PASSED" << endl;

 59     cout << "=======================================" << endl;

 60   }

 61   done = 1;

 62   // Just wait for few cycles

 63   wait(100);

 64 }

SystemC Exports

  1 #ifndef MEMORY_TB_EXPORTS_H

  2 #define MEMORY_TB_EXPORTS_H

  3 

  4 #ifdef __cplusplus

  5 extern "C" {

  6 #endif

  7 

  8 void init_sc     ();

  9 void exit_sc     ();

 10 void sample_hdl  (void *Invector);

 11 void drive_hdl   (void *Outvector);

 12 void advance_sim (unsigned long simtime);

 13 void exec_sc     (void *invector, void *outvector, unsigned long simtime);

 14 

 15 #ifdef __cplusplus

 16 }

 17 #endif

 18 

 19 #endif

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