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eSilicon Vietnam - Physical Design Engineers

eSilicon Vietnam - Software Testing Engineer

eSilicon Vietnam

eTown 2, 9th Floor, 364 Cong Hoa Street, Tan Binh District

Job Level: Nhân viên

eSilicon is an innovative fabless semiconductor company that has pioneered a new business model called Value Chain Producer(VCP). The company provides an extensive suite of ASIC services and solutions aimed at delivering a flexible, low-cost and lower-risk path to volume chip production. The key is our integrated and flexible approach that incorporates ASIC design, productization and manufacturing services into a seamless environment, all brought together by the company’s patented infrastructure that enables superior predictability and faster time-to-market advantages for our customers


SDS is unique amongst semiconductor IP companies in providing IP that fits seamlessly into your internal flow. Tested and proven using your own methodology and test practices, the IP we deliver is indistinguishable from that created by your internal team. Leveraging our 10+ years of experience we work closely with our customers to deliver leading edge semiconductor IP to our clients. We can customize our solutions to cater for your specific market requirements and for your specific process.

Qui mô công ty: 100-499

Website: http://www.esilicon.com

 

Work Location

Ho Chi Minh

Job Level

Mới tốt nghiệp/Thực tập sinh

Job Category

Điện/Điện tử
IT-Phần cứng/Mạng
Viễn Thông

Preferred Language

English

 

Job description

Summary

Our Physical Design Engineers are mainly responsible for the physical design flow from Netlist to GDSII, physical synthesis, verification and finalization for the design.
Responsibilities include:

- Audit customer design for PnR processing
- Perform physical design flow from Netlist to GDSII with timing closure, DRC clean: Audit Netist/ timing constraints; Clock tree synthesis and Hold fixing; Routing and post routing optimization
- Timing sign-off: Timing clean database with timing signoff tools
- Synthesis & Floor planning, Power structure designing

 

Job requirement

- Hands on experience with detailed exposure to an actual SoC physical design in STA

- Floor-Planning

- Power Analysis

- CTS

- Routing

- DRC/LVS

- Noise Analysis

- Use of Magma or Synopsys ASIC physical design tools (Synopsys ICC, Talus or other P&R tools)

- Scripting language with Perl, Tk/Tcl, AWK experiences strong plus

- BS of Electronics, Telecommunication, Physical - Electronics, Computer Science, Hardware Engineering

- English communication skills

 

 
Theo vietnamworks
 

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