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Thế giới ASIC

BIST - Built-in-self-Test

BIST generates its own stimulus and analyzes its own response.  BIST is used normally to validate a product in labs, there are different kind of BIST used in system to validate.
one of the method is , using LFSR, LFSR generates random stimulus and it is expected that chip is in its normal functional mode. with the configuration, with LFSR ,
Lần cập nhật cuối ( Thứ năm, 07 Tháng 10 2021 13:52 ) Đọc thêm...
 

(UPF) Unified Power Format

Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.
Lần cập nhật cuối ( Thứ năm, 07 Tháng 10 2021 13:50 ) Đọc thêm...
 

Running Disparity

In order to create a DC-balanced data stream, the concept of disparity is employed to balance the number of 0s and 1s. 

The disparity of a block is calculated by the number of 1s minus the number of 0s. The value of a block that has a zero disparity is called disparity neutral. If both the 4-bit and 6-bit blocks are disparity neutral, a combined 10-bit encoded data will be disparity neutral as well. This will create a perfect DC-balanced code. 
Lần cập nhật cuối ( Thứ ba, 05 Tháng 10 2021 13:40 ) Đọc thêm...
 

Async Reset or Sync Reset for ASIC ?


Q ASYNC OR SYNC RESET? which one is use more in ASIC industry?

Async reset with sync release is probably the most common. Sync reset is used occasionally though. Async has the obvious advantage that your PoR works before the clock is working. You need a sync release to avoid potential metastability and make sure FSM start in a consistent state.
Lần cập nhật cuối ( Thứ ba, 05 Tháng 10 2021 13:35 ) Đọc thêm...
 

Handling multiclock domain in design ( RTL + SDC )

In today world, it is most likely design having multiple clocks and there will be signals crossing between those clock domain.  The one way to design such logic is writing FSM in both clock domain and keep request/ack mechanism. Request must be synchronized in destination clock domain and acknowledge must also be sync in destination clock.
Lần cập nhật cuối ( Thứ ba, 05 Tháng 10 2021 13:32 ) Đọc thêm...
 

Key Points in Mixed Signal Design Verification

Introduction:

A Mixed Signal Interface could be a high speed interface where data is transferred between two devices through a medium. Transmitting data is not big issue but receiving data contribute major part of its performance. Key points/block for high speed and high performance mixed signals are described in below sections.
Lần cập nhật cuối ( Chủ nhật, 03 Tháng 10 2021 16:53 ) Đọc thêm...
 

Unateness Positive Unate and Negative Unate

Each cell in design will have timing arcs, there are different types of arcs present in design. For example, for sequential cell , timing arc will be from clock to Q , for Combi logic, timing arc will be from input to output.
Lần cập nhật cuối ( Chủ nhật, 03 Tháng 10 2021 16:43 ) Đọc thêm...
 

Synchronizers list dump using SpyGlass Tool

This section will tell you how to dump the list of sync cell using spyglass tool.

There are complexities and different settings which depends on design to design, some fine tuning may require to dump the Synchronizer list.


Spyglass give a lot of options which vary design to design, below are the common settings you can use in spyglass project file.
Lần cập nhật cuối ( Chủ nhật, 03 Tháng 10 2021 16:00 ) Đọc thêm...
 

Asynchronous FIFO with Programmable Depth

Asynchronous FIFO Design
Asynchronous FIFO Verilog Code
Asynchronous FIFO with block diagram and verilog Code.
Lần cập nhật cuối ( Thứ bảy, 02 Tháng 10 2021 15:47 ) Đọc thêm...
 

Verilog code for parity checker (even parity/odd parity)

In the case of even parity, the number of bits whose value is 1 in a given set are counted. If that total is odd, the parity bit value is set to 1, making the total count of 1's in the set an even number. If the count of ones in a given set of bits is already even, the parity bit's value remains 0.

Lần cập nhật cuối ( Thứ bảy, 02 Tháng 10 2021 15:43 ) Đọc thêm...
 

Verilog code to detect Pattern

Detecting pattern is come in Digital design and it is most commonly question during the interview.

Here is one example of detecting " 100110 " pattern using a FSM.
Lần cập nhật cuối ( Thứ bảy, 02 Tháng 10 2021 15:38 ) Đọc thêm...
 

Low Power Design and Verification

Low power design is not a new area, but it was not that much important as it is now.
Semiconductor market trend is very fast changing , and it is a challenge to face and ready with new technology.
Lần cập nhật cuối ( Thứ ba, 28 Tháng 9 2021 14:59 ) Đọc thêm...
 

Convergence , divergence and re-convergence

Now a days , multiple clocks in a system are common due to increasing frequency and complexity. A CDC check is a must check on the design before tapping out as any CDC violation may be fatal and could be a cause of chip failure.
Lần cập nhật cuối ( Thứ ba, 28 Tháng 9 2021 14:45 ) Đọc thêm...
 

WEIGHTED DISTRIBUTION IN SYSTEM VERILOG

In constraint random verification, it may take a long time for a particular corner case to be generated which scenario we never thought. Sometimes even after running test-case regression for N number of time corner case may not be generated and you may see holes in functional coverage.

Lần cập nhật cuối ( Thứ ba, 28 Tháng 9 2021 14:41 ) Đọc thêm...
 

CONSTRAINT OVERRIDE IN SYSTEM VERILOG

Here in this overriding of constraint if we will have the same constraint name in the parent class as well as child class then we can say that our constraint is overridden in the child class.

Lần cập nhật cuối ( Chủ nhật, 26 Tháng 9 2021 20:12 ) Đọc thêm...
 

DIFFERENT ARRAY TYPES AND QUEUES IN SYSTEM VERILOG

Dynamic Array: Usage of dynamic array when user to allocate its size for storage during run time.Dynamic array store a contiguous collection of data.

Lần cập nhật cuối ( Chủ nhật, 26 Tháng 9 2021 20:09 ) Đọc thêm...
 
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