Trung tâm đào tạo thiết kế vi mạch Semicon


  • ĐĂNG KÝ TÀI KHOẢN ĐỂ TRUY CẬP NHIỀU TÀI LIỆU HƠN!
  • Đăng ký
    *
    *
    *
    *
    *
    Fields marked with an asterisk (*) are required.
semi1_solvingproblems.jpg

Thế giới ASIC

STREAMING OPERATOR IN SYSTEMVERILOG

The streaming operator uses the terminology pack when you take multiple variables and stream them into a single variable. And conversely, unpack is when you stream a single variable into multiple variables.

Đọc thêm...
 

Running Disparity

In order to create a DC-balanced data stream, the concept of disparity is employed to balance the number of 0s and 1s. 

The disparity of a block is calculated by the number of 1s minus the number of 0s. The value of a block that has a zero disparity is called disparity neutral. If both the 4-bit and 6-bit blocks are disparity neutral, a combined 10-bit encoded data will be disparity neutral as well
Lần cập nhật cuối ( Thứ ba, 17 Tháng 8 2021 13:30 ) Đọc thêm...
 

DIFFERENT ARRAY TYPES AND QUEUES IN SYSTEM VERILOG

Dynamic Array: Usage of dynamic array when user to allocate its size for storage during run time.

Dynamic array store a contiguous collection of data.

The array indexing should be always integer type.

Đọc thêm...
 

(UPF) Unified Power Format

VLSI Digital Design Interview Questions

Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.

Lần cập nhật cuối ( Thứ bảy, 26 Tháng 6 2021 20:23 ) Đọc thêm...
 

MicroWire Interface

MICROWIRE is a simple three-wire serial communications interface. This standard protocol handles serial communications between controller and peripheral devices. In this application note are some clarifications of MICROWIRE logical operation and of hardware and software considerations. A typical communication on the Microwire bus is made through the CS, SK, DI and DO signals.
Lần cập nhật cuối ( Thứ ba, 22 Tháng 6 2021 14:19 ) Đọc thêm...
 

PCI-Express - Overview

PCI Express ( Peripheral Component Interconnect Express ),  is a high speed serial computer expansion bus standard. It is designed to replace the older version of PCI like PCI/PCI-X standard.

Difference in Normal Pci and Pci-Express -> 
Lần cập nhật cuối ( Thứ ba, 17 Tháng 8 2021 13:30 ) Đọc thêm...
 

ADVANTAGES OF UVM OVER SV

UVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology in terms of architecting testbenches and test cases, and also comes with a library of classes that helps in building efficient constrained random testbenches easily.

Lần cập nhật cuối ( Thứ ba, 22 Tháng 6 2021 13:58 ) Đọc thêm...
 

INHERITANCE IN SYSTEMVERILOG OOPS

Inheritance in SystemVerilog is the most commonly used principles of Object Oriented Programming (OOP) that facilitates reuse. It’s called Inheritance because it creates new classes taking all the existing Properties and Methods from the Base Class or Super Class.

Lần cập nhật cuối ( Thứ ba, 22 Tháng 6 2021 13:59 ) Đọc thêm...
 

GENERATE RANDC BEHAVIOR FROM RAND VARIABLE

It’s easy to get the first cycle of random numbers by pushing values on a list in post_randomize() and adding a constraint that keeps the values in the list excluded from the next solution.

Đọc thêm...
 

SYSTEM VERILOG ASSERTION BINDING (SVA BIND)

Now a days we use to deal with modules of Verilog or VHDL or combination of both. Mostly verification engineers are not allowed to modified these modules. But still SVA addition to these modules are required and easy to verify lot of RTL functionality. How can you add SVA to these modules?  Let’s find out !!

Đọc thêm...
 

GENERAL QUESTIONS ON COVERAGE:

1. What is the difference between code coverage and functional coverage?

There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification process.

Lần cập nhật cuối ( Thứ năm, 17 Tháng 6 2021 16:45 ) Đọc thêm...
 

ENABLE/DISABLE SPECIFIC CONSTRAINT

In below example we can understand how we can enable or disable a specific constraint whenever we need to do.

Đọc thêm...
 

RAISE/DROP OBJECTION AUTOMATICALLY WITH UVM

Variable uvm_sequence_base::starting_phase is deprecated and replaced by two new methods set_starting_phase and get_starting_phase, which prevent starting_phase from being modified in the middle of a phase. This change is not backward-compatible with UVM 1.1,

Đọc thêm...
 

SOC VERIFICATION FLOW

Many people do not appreciate what makes a system-on-chip (SoC) different from other semiconductor devices. Many companies, especially in electronic design automation (EDA), toss around the term “SoC” without defining it or explaining why it’s such an important concept.

Đọc thêm...
 

UVM SEQUENCE ARBITRATION MECHANISM

Multiple sequences can interact concurrently with a driver connected to a single interface. The sequencer supports an arbitration mechanism to ensure that at any point of time only one sequence has access to the driver. The choice of which sequence can send a sequence_item is dependent on a user selectable sequencer arbitration algorithm. 

Đọc thêm...
 

HOW UVM CALLBACK WORKS?

Callback mechanism is used for altering the behavior of the transactor/BFM without modifying the existing BFM/transactor. Callback gives flexibility to plug-and-play and reuse the components i.e. driver, monitor etc.. 

Lần cập nhật cuối ( Chủ nhật, 13 Tháng 6 2021 12:46 ) Đọc thêm...
 
Trang 10 của 109

Các bài viết mới nhất

CÁC BÀI VIẾT LIÊN QUAN

Các bài viết xem nhiều nhất