Trung tâm đào tạo thiết kế vi mạch Semicon


  • ĐĂNG KÝ TÀI KHOẢN ĐỂ TRUY CẬP NHIỀU TÀI LIỆU HƠN!
  • Đăng ký
    *
    *
    *
    *
    *
    Fields marked with an asterisk (*) are required.
semi4_volunteering.jpg

Thế giới ASIC

Verilog code for 8b/10b encoder and decoder

8b/10b is used mainly for clock recovery in serial communication. With this coding, the serial line will always get a balanced stream of 0's and 1's which give enough switching of 0's and 1's level on the line. It is called DC balancing.
Using this encoding will result in 25% overhead in the data stream , meaning to transmit 80-bits , you will actually transmit 100-bits.
Lần cập nhật cuối ( Chủ nhật, 26 Tháng 9 2021 20:04 ) Đọc thêm...
 

Serial Peripheral Interface - SPI

Serial Peripheral Interface - SPI
(adsbygoogle = window.adsbygoogle || []).push({ google_ad_client: "ca-pub-9050238130712788", enable_page_level_ads: true }); Serial Peripheral Interface Bus
Lần cập nhật cuối ( Thứ bảy, 25 Tháng 9 2021 14:07 ) Đọc thêm...
 

A Sample file for Synthesis

Design Specification 
A counter having 2 input clocks, clk_a running at 100 MHz and clk_B running at  200MHz.
there are clock divider for clk_A in design.
Lần cập nhật cuối ( Thứ bảy, 25 Tháng 9 2021 14:03 ) Đọc thêm...
 

Verilog code for parity checker

In the case of even parity, the number of bits whose value is 1 in a given set are counted. If that total is odd, the parity bit value is set to 1, making the total count of 1's in the set an even number. If the count of ones in a given set of bits is already even, the parity bit's value remains 0.
In the case of odd parity, the situation is reversed. Instead, if the sum of bits with a value of 1 is odd, the parity bit's value is set to zero.

Lần cập nhật cuối ( Thứ bảy, 25 Tháng 9 2021 13:54 ) Đọc thêm...
 

SEMAPHORE IN SYSTEMVERILOG

A semaphore allows you to control access to a resource.

Conceptually, a semaphore is a bucket. When a semaphore is allocated, a bucket that contains a fixed number of keys is created.

Lần cập nhật cuối ( Thứ năm, 23 Tháng 9 2021 14:32 ) Đọc thêm...
 

WEIGHTED DISTRIBUTION IN SYSTEM VERILOG

In constraint random verification, it may take a long time for a particular corner case to be generated which scenario we never thought. Sometimes even after running test-case regression for N number of time corner case may not be generated and you may see holes in functional coverage. 

Lần cập nhật cuối ( Thứ năm, 23 Tháng 9 2021 14:17 ) Đọc thêm...
 

PCI Express - Overview

PCI Express ( Peripheral Component Interconnect Express ),  is a high speed serial computer expansion bus standard. It is designed to replace the older version of PCI like PCI/PCI-X standard.
Difference in Normal Pci and Pci-Express -> 
Lần cập nhật cuối ( Thứ năm, 23 Tháng 9 2021 13:50 ) Đọc thêm...
 

DIGITAL VERIFICATION


Functional Verification is often the most resource intensive and costly part of the SoC hardware design process. Semicon’s engineering team can starting verification early in the design cycle by streamlining testbench development, facilitating faster turnaround times and high quality, reliable designs.

Semicon’s expertise covers a comprehensive range of skills including test plan creation, testbench development and design debug at both IP block and SoC level. We are able to bring the latest testbench verification methodologies such as UVM VIP development, ABV and metric driven verification.

- Feature extraction from Specification.
- Develop test plan which includes stimulus generation plan, functionality checking and coverage modeling.
- Review the test plan with Design team.
- Develop testbench environment and other components for verifying each block in design.
- Create necessary test cases to ensure desired functionality of each block.
- Run Regression tests at block level and report bugs in RTL.
- Create directed and randomized test cases to check corner cases in design.
- Integrate all blocks and reuse block level verification components to verify the design at system level.
- Run tests at system level to ensure correct block integration. Proceed with system level regression testing to verify system functionality and generate coverage reports.
 

ADVANTAGES OF UVM OVER SV

UVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology in terms of architecting testbenches and test cases, and also comes with a library of classes that helps in building efficient constrained random testbenches easily.

Lần cập nhật cuối ( Chủ nhật, 19 Tháng 9 2021 16:10 ) Đọc thêm...
 

HOW TO TERMINATE UVM TEST? (UVM OBJECTIONS)

As we know that in Traditional Directed Testbenches, we used to terminate a Test by calling a Verilog System Task i.e. $finish after the required steps like reset, configuration, data transfer and self-checking are completed.

Lần cập nhật cuối ( Chủ nhật, 19 Tháng 9 2021 16:08 ) Đọc thêm...
 

WEIGHTED DISTRIBUTION IN SYSTEM VERILOG

In constraint random verification, it may take a long time for a particular corner case to be generated which scenario we never thought. Sometimes even after running test-case regression for N number of time corner case may not be generated and you may see holes in functional coverage.

Lần cập nhật cuối ( Chủ nhật, 19 Tháng 9 2021 16:05 ) Đọc thêm...
 

RANDCASE VS RANDSEQUENCE IN SYSTEMVERILOG

Randcase: Randcase is a case statement that randomly selects one of its branches just like a case statement in Verilog but here as its randcase so it will pick statements randomly. Randcase can be used in class or modules.

Lần cập nhật cuối ( Thứ bảy, 18 Tháng 9 2021 13:45 ) Đọc thêm...
 

STATIC AND AUTOMATIC LIFETIME

Static: For a variable static lifetime is, its memory never de-allocated until simulation ends. Automatic: For a variable Automatic lifetime is, it is stack storage of variable (for multiple entries to a task, function, or block,

Lần cập nhật cuối ( Thứ bảy, 18 Tháng 9 2021 13:39 ) Đọc thêm...
 

WEIGHTED DISTRIBUTION IN SYSTEM VERILOG

In constraint random verification, it may take a long time for a particular corner case to be generated which scenario we never thought. Sometimes even after running test-case regression for N number of time corner case may not be generated and you may see holes in functional coverage.

Lần cập nhật cuối ( Thứ bảy, 18 Tháng 9 2021 13:31 ) Đọc thêm...
 

GENERATE RANDC BEHAVIOR FROM RAND VARIABLE

It’s easy to get the first cycle of random numbers by pushing values on a list in post_randomize() and adding a constraint that keeps the values in the list excluded from the next solution.

Lần cập nhật cuối ( Thứ năm, 16 Tháng 9 2021 18:46 ) Đọc thêm...
 

TYPES OF COVERAGE METRICS

Coverage is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of constrained random testbenches. 

Lần cập nhật cuối ( Thứ năm, 16 Tháng 9 2021 18:43 ) Đọc thêm...
 
Trang 3 của 109

Các bài viết mới nhất

CÁC BÀI VIẾT LIÊN QUAN

Các bài viết xem nhiều nhất